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tests/acceptance: Skip slow quanta-gsj U-boot+Linux test
2020-09-09
Bin Meng
hw/
r
is
c
v: So
r
t
the Kconfig
o
ptio
n
s
i
n
a
l
p
h
abe
t
i
c
a
l
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv
:
Dro
p
C
ONFIG_
S
IFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: Always b
u
ild
r
is
c
v_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ri
s
c
v
: M
o
ve sifi
v
e_
t
es
t
m
o
d
e
l to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
M
o
ve
sifive_uart
m
odel to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Men
g
hw/riscv: Move
riscv_htif model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w
/riscv:
Move sifive_plic mode
l
to
h
w/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w/
r
i
s
cv: Move sifive
_
clint m
o
del to hw/
i
n
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/r
i
scv:
M
ove sifive_g
p
i
o
model to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv:
Move si
f
i
v
e
_u_otp
model to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
eng
hw/riscv: Move
s
if
i
ve_u
_
prci model
t
o hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifi
v
e_e_prci model
to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: sif
i
ve_u: C
o
nnect a
DMA co
n
troller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: clint: Avoid usin
g
h
a
rd-coded
timebase fre
q
uency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: microch
i
p_pfsoc: Hook
GPIO control
l
e
rs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/
r
i
s
cv: microchip_pfsoc
:
Connect 2 Cadence GE
M
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
hw/arm:
x
lnx:
S
et a
l
l
boards' GEM '
p
hy-addr' propert
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
h
w/net: c
a
dence_ge
m
: Add a new
'phy-addr' p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
hw/riscv:
m
icrochip_pfs
o
c: Co
n
nect a DMA con
t
roller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/dma: Add
S
iFive platfor
m
DMA contr
o
ller em
u
lation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv:
micr
o
chip_pfso
c
: Connect a
C
adence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
h
w
/sd:
A
dd Cadence
S
DHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: micr
o
chip_pfsoc:
C
onnect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
c
h
ar:
A
dd Micr
o
chip PolarFire SoC
M
MUART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w/riscv
:
In
i
tial su
p
port
f
or Microchip Pola
r
Fire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: cpu: Set reset vector based on the configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
h
w/riscv: har
t
: A
d
d a ne
w
'resetve
c
' prope
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
tar
g
e
t
/riscv
:
cpu
:
Add a new 'resetv
e
c' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n
M
e
ng
g
itlab-ci/ope
n
sbi: Update GitLab CI t
o
build
g
eneri
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
h
w
/riscv: spike: Chan
g
e
t
he default b
i
os to use g
e
neric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/riscv: Use pre-
b
u
i
lt bios
i
mage of generic pl
a
tfor
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
roms
/
Mak
e
file: Build
the ge
n
eric plat
f
orm for RIS
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
roms/opensbi:
Upg
r
a
d
e
f
rom v0
.
7
t
o
v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
c
o
nfigu
r
e: Cre
a
te symbolic l
i
nks for pc-bi
o
s/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sif
i
ve_u: A
d
d a dumm
y
L2 cache controll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
in Meng
hw/sd: Cor
r
e
c
t t
h
e maxi
m
um size of a
Standard Ca
p
a
c
i
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
Fix incorre
c
t pop
u
lated function swit
c
h statu
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin M
e
ng
hw/r
i
scv: s
i
five
_
e:
C
orrect debug block s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n
Meng
hw/riscv:
M
odify MROM si
z
e to end at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv: virt
:
Sort the SoC memma
p
t
a
ble entr
i
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Meng
MAI
N
TAINER
S
: Add an entry for
O
penSBI fir
m
ware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw/riscv:
s
ifive_u: Add a dummy DDR
m
em
o
ry contr
o
ller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifi
v
e_u
:
So
r
t th
e
S
o
C
memmap table entri
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
five_u: S
u
pp
o
r
t diffe
r
e
n
t
bo
o
t source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/riscv: sifive: Change SiFi
v
e E/U CPU reset
v
ec
t
or
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target
/
ris
c
v: Ren
a
me
I
B
E
X CPU init ro
u
ti
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw
/
riscv: sif
i
ve_u: Ad
d
a
new
p
roperty msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
h
w
/riscv: sifive_u: Re
n
ame serial property get
/
s
e
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv:
sifive_u: Add
r
eset functi
o
nality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/
r
iscv
:
sifive_gpio: Do not
b
lindly
t
rigger o
u
tput
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifiv
e
_u:
Hook a GPIO cont
r
olle
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: sifi
v
e_gpio: Add
a ne
w
'ngpio'
propert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv: sifive_g
p
i
o:
C
le
a
n
up t
h
e codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv:
s
ifi
v
e_u: Genera
t
e device tree node fo
r
O
TP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u
:
Simplify
the
GEM IRQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/ris
c
v: open
t
i
t
a
n:
Rem
o
ve
t
h
e riscv_ p
r
efix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw
/
r
is
c
v
: sifive
_
e: Remove
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv:
K
eep the CPU init rou
t
ine names consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Genera
l
ize CPU
init routine for
t
h
e imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v
: Gener
a
lize CPU i
n
it routine fo
r
t
he gcsu
C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
riscv: General
i
ze
C
PU init
ro
u
tine for the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/risc
v
: virt: Rem
o
ve the ri
s
c
v_ prefix of the
machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Men
g
hw/riscv: sifive_u: Remove th
e
riscv_ p
r
e
fix of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Me
n
g
riscv: Ch
a
n
g
e
t
h
e default behavi
o
r if
n
o -
b
ios op
t
ion
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
risc
v
: Suppress
t
he err
o
r report
f
or QEMU testing wi
t
h
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
rom
s
: opensbi: Upgra
d
e from v0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/r
i
scv: G
e
nerate correct "mmu-t
y
pe" for 32-bit
ma
c
hines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin M
e
ng
riscv/sifive_u: Add a serial property t
o
the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
Me
n
g
gitlab-c
i
.
yml: Add
jobs to
b
u
i
l
d OpenSBI firmware bina
r
ies
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n
M
e
n
g
ri
s
c
v: sifive_u: Update BIOS
_
F
IL
E
NAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
in Meng
roms: opens
b
i: A
d
d 32-bit firmw
a
re image for sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
r
o
ms: opensbi:
U
pgr
a
de fr
o
m
v
0
.
5
t
o
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Meng
hw:
net: cadenc
e
_
gem: Fix build erro
r
s in DB
_
PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: v
i
rt: Allo
w
PCI addres
s
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Me
n
g
riscv:
sifive
_
u:
Add
e
thern
e
t0 to
t
he ali
a
se
s
node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin
M
en
g
ris
c
v: hw
:
Drop "cloc
k
-
frequ
e
ncy"
property of
cpu node
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
B
in Meng
risc
v
: Skip c
h
e
c
king CSR p
r
ivil
e
ge lev
e
l in debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifive_u: Update m
o
del and co
m
p
a
tible st
r
ings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
riscv: sifive_u: Remove handcr
a
fted
clo
c
k nod
e
s fo
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
ri
s
cv: sifive_u: Fix broken GE
M
suppor
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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2019-09-17
Bin M
e
ng
riscv:
sifive_
u
:
I
nsta
n
tiate OTP memory
w
it
h
a ser
i
a
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
B
in Meng
riscv:
s
ifiv
e
: Imple
m
ent a model
f
or SiF
i
ve
FU
5
40 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
B
i
n Meng
riscv: roms:
Update def
a
ult
bios for si
f
ive_u machin
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
|
tree
2019-09-17
Bin Meng
riscv: si
f
ive_u: Change UART node name in devi
c
e tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin M
e
n
g
r
i
scv:
s
ifive_u: Upda
t
e UA
R
T
b
ase addresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bi
n
Meng
riscv: sifive_u:
R
efe
r
e
nce PRCI clocks in U
A
R
T
and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv:
sifive_
u
: Add PRCI block to the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin
M
e
n
g
riscv:
s
ifive_u: Gener
a
te
hfclk and rtcclk
nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin
Meng
riscv: sifive:
Impl
e
ment PRCI mo
d
el for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bi
n
Meng
ri
s
cv: sifiv
e
_u: Update PLIC hart
topology configuration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
si
f
ive_u: Update har
t
configuration
t
o ref
l
e
c
t
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
riscv
:
sif
i
ve_u:
Set the minimum number of
c
pus to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: hart: Add a "hart
i
d-ba
s
e" property to RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: hart:
E
x
tract
h
art rea
l
i
z
e to a sep
a
rate rout
i
ne
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
A
dd a s
i
five_cpu
.
h
to
i
n
c
l
ud
e
both
E and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in M
e
ng
risc
v
: sif
i
ve
_
e:
Drop sifive
_
mmio_emula
t
e()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: sifive_
e
: prci: U
p
date
the P
R
CI r
e
gister
b
lock
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_e:
p
rci:
F
ix a typ
o
o
f
hfxosccfg regi
s
ter
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: s
i
fiv
e
: Renam
e
sifive
_
prci
.
{c, h}
to sifive_e
_
pr
c
i
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive_u: Remove the unneces
s
ary include of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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