| commit | 495134b75cca3e6a34d4233113c5143439061771 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Tue, 16 Jun 2020 00:50:38 +0000 (15 17:50 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 19 Jun 2020 15:25:27 +0000 (19 08:25 -0700) | ||
| tree | 48a0fbb22149134b29b7a7345c4a3a63b169accf | treesnapshot (tar.gz zip) |
| parent | e8905c6ce86f5023f6814abd7c72a809e5d018ec | commitdiff |
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/sifive_e.c | diffblobblamehistory | |
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| target/riscv/cpu.c | diffblobblamehistory |