| commit | 20f41c869830fdf0ac9aec8d14b766167f47ce7d | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:20:02 +0000 (6 09:20 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:46 +0000 (17 08:42 -0700) | ||
| tree | 81d6ea4c4356d23ae2294e1c98f6f6112b43c31d | treesnapshot (tar.gz zip) |
| parent | 68c9a9b3eb5897bf39e6aa0aa72e5761f3bc9725 | commitdiff |
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| include/hw/riscv/sifive_cpu.h | [new file with mode: 0644] | blob |
| include/hw/riscv/sifive_e.h | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |