| commit | 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Thu, 3 Sep 2020 10:40:14 +0000 (3 18:40 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 9 Sep 2020 22:54:19 +0000 (9 15:54 -0700) | ||
| tree | 2e1a7c7e45eff69893f38bc9cb7448385b5a21b9 | treesnapshot (tar.gz zip) |
| parent | 9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae | commitdiff |
hw/riscv: Move sifive_u_otp model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>