| commit | 621c1006d2d82da9f266f21ad8e887c38769a11b | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Mon, 8 Jun 2020 14:17:37 +0000 (8 07:17 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 19 Jun 2020 15:25:27 +0000 (19 08:25 -0700) | ||
| tree | aa8f0f30f8d1082f9f2a1255568850ead7f49285 | treesnapshot (tar.gz zip) |
| parent | 8a88b9f54f5fb2acecf73760903b1f58fb40d0cd | commitdiff |
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/sifive_gpio.c | diffblobblamehistory |