| commit | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Tue, 1 Sep 2020 01:38:57 +0000 (1 09:38 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 9 Sep 2020 22:54:18 +0000 (9 15:54 -0700) | ||
| tree | 8976db8de135bd8097e8902b4c261d3988893ee5 | treesnapshot (tar.gz zip) |
| parent | 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511 | commitdiff |
hw/riscv: hart: Add a new 'resetvec' property
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/riscv_hart.c | diffblobblamehistory | |
| include/hw/riscv/riscv_hart.h | diffblobblamehistory |