| commit | 0d95299468c8f19a306b93bb9b6940ea55945db5 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:20:08 +0000 (6 09:20 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:47 +0000 (17 08:42 -0700) | ||
| tree | 15b4eaa6206b97d9f17b37aba661496b73b7df9f | treesnapshot (tar.gz zip) |
| parent | ef965ce23956a9e5cde5c9e91081484ec68a4139 | commitdiff |
riscv: sifive: Implement PRCI model for FU540
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/Makefile.objs | diffblobblamehistory | |
| hw/riscv/sifive_u_prci.c | [new file with mode: 0644] | blob |
| include/hw/riscv/sifive_u_prci.h | [new file with mode: 0644] | blob |