| commit | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Thu, 3 Sep 2020 10:40:16 +0000 (3 18:40 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 9 Sep 2020 22:54:19 +0000 (9 15:54 -0700) | ||
| tree | ee4ed77217e62a3d3a8c185e8eda59ff2a138c35 | treesnapshot (tar.gz zip) |
| parent | 4921a0ce86cecd03e6918832673db79de62e6fe1 | commitdiff |
hw/riscv: Move sifive_clint model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>