?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/riscv: Move sifive_clint model to hw/intc
[qemu/ar7.git] / hw / riscv / microchip_pfsoc.c
blob131eea1ef3820635a5e852e742f1d489fb3f72c9
1 /*
2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
10 *
11 * 0) CLINT (Core Level Interruptor)
12 * 1) PLIC (Platform Level Interrupt Controller)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it
16 * 5) SiFive Platform DMA (Direct Memory Access Controller)
17 * 6) GEM (Gigabit Ethernet MAC Controller)
18 *
19 * This board currently generates devicetree dynamically that indicates at least
20 * two harts and up to five harts.
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms and conditions of the GNU General Public License,
24 * version 2 or later, as published by the Free Software Foundation.
25 *
26 * This program is distributed in the hope it will be useful, but WITHOUT
27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
29 * more details.
30 *
31 * You should have received a copy of the GNU General Public License along with
32 * this program. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35 #include "qemu/osdep.h"
36 #include "qemu/error-report.h"
37 #include "qemu/log.h"
38 #include "qemu/units.h"
39 #include "qemu/cutils.h"
40 #include "qapi/error.h"
41 #include "hw/boards.h"
42 #include "hw/irq.h"
43 #include "hw/loader.h"
44 #include "hw/sysbus.h"
45 #include "chardev/char.h"
46 #include "hw/cpu/cluster.h"
47 #include "target/riscv/cpu.h"
48 #include "hw/misc/unimp.h"
49 #include "hw/riscv/boot.h"
50 #include "hw/riscv/riscv_hart.h"
51 #include "hw/riscv/sifive_plic.h"
52 #include "hw/riscv/microchip_pfsoc.h"
53 #include "hw/intc/sifive_clint.h"
54 #include "sysemu/sysemu.h"
55
56 /*
57 * The BIOS image used by this machine is called Hart Software Services (HSS).
58 * See https://github.com/polarfire-soc/hart-software-services
59 */
60 #define BIOS_FILENAME "hss.bin"
61 #define RESET_VECTOR 0x20220000
62
63 /* CLINT timebase frequency */
64 #define CLINT_TIMEBASE_FREQ 1000000
65
66 /* GEM version */
67 #define GEM_REVISION 0x0107010c
68
69 static const struct MemmapEntry {
70 hwaddr base;
71 hwaddr size;
72 } microchip_pfsoc_memmap[] = {
73 [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
74 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
75 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
76 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
77 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
78 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
79 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
80 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
81 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
82 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
83 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
84 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
85 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
86 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
87 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
88 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
89 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
90 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
91 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
92 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
93 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
94 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
95 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
96 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
97 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
98 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
99 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
100 [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
101 [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
102 };
103
104 static void microchip_pfsoc_soc_instance_init(Object *obj)
105 {
106 MachineState *ms = MACHINE(qdev_get_machine());
107 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
108
109 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
110 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
111
112 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
113 TYPE_RISCV_HART_ARRAY);
114 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
115 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
116 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
117 TYPE_RISCV_CPU_SIFIVE_E51);
118 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
119
120 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
121 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
122
123 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
124 TYPE_RISCV_HART_ARRAY);
125 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
126 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
127 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
128 TYPE_RISCV_CPU_SIFIVE_U54);
129 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
130
131 object_initialize_child(obj, "dma-controller", &s->dma,
132 TYPE_SIFIVE_PDMA);
133
134 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
135 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
136
137 object_initialize_child(obj, "sd-controller", &s->sdhci,
138 TYPE_CADENCE_SDHCI);
139 }
140
141 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
142 {
143 MachineState *ms = MACHINE(qdev_get_machine());
144 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
145 const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
146 MemoryRegion *system_memory = get_system_memory();
147 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
148 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
149 MemoryRegion *envm_data = g_new(MemoryRegion, 1);
150 char *plic_hart_config;
151 size_t plic_hart_config_len;
152 NICInfo *nd;
153 int i;
154
155 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
156 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
157 /*
158 * The cluster must be realized after the RISC-V hart array container,
159 * as the container's CPU object is only created on realize, and the
160 * CPU must exist and have been parented into the cluster before the
161 * cluster is realized.
162 */
163 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
164 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
165
166 /* E51 DTIM */
167 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
168 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
169 memory_region_add_subregion(system_memory,
170 memmap[MICROCHIP_PFSOC_E51_DTIM].base,
171 e51_dtim_mem);
172
173 /* Bus Error Units */
174 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
175 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
176 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
177 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
178 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
179 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
180 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
181 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
182 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
183 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
184 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
185 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
186 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
187 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
188 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
189
190 /* CLINT */
191 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
192 memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
193 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
194 CLINT_TIMEBASE_FREQ, false);
195
196 /* L2 cache controller */
197 create_unimplemented_device("microchip.pfsoc.l2cc",
198 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
199
200 /*
201 * Add L2-LIM at reset size.
202 * This should be reduced in size as the L2 Cache Controller WayEnable
203 * register is incremented. Unfortunately I don't see a nice (or any) way
204 * to handle reducing or blocking out the L2 LIM while still allowing it
205 * be re returned to all enabled after a reset. For the time being, just
206 * leave it enabled all the time. This won't break anything, but will be
207 * too generous to misbehaving guests.
208 */
209 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
210 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
211 memory_region_add_subregion(system_memory,
212 memmap[MICROCHIP_PFSOC_L2LIM].base,
213 l2lim_mem);
214
215 /* create PLIC hart topology configuration string */
216 plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
217 ms->smp.cpus;
218 plic_hart_config = g_malloc0(plic_hart_config_len);
219 for (i = 0; i < ms->smp.cpus; i++) {
220 if (i != 0) {
221 strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
222 plic_hart_config_len);
223 } else {
224 strncat(plic_hart_config, "M", plic_hart_config_len);
225 }
226 plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
227 }
228
229 /* PLIC */
230 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
231 plic_hart_config, 0,
232 MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
233 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
234 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
235 MICROCHIP_PFSOC_PLIC_PENDING_BASE,
236 MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
237 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
238 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
239 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
240 memmap[MICROCHIP_PFSOC_PLIC].size);
241 g_free(plic_hart_config);
242
243 /* DMA */
244 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
245 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
246 memmap[MICROCHIP_PFSOC_DMA].base);
247 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
248 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
249 qdev_get_gpio_in(DEVICE(s->plic),
250 MICROCHIP_PFSOC_DMA_IRQ0 + i));
251 }
252
253 /* SYSREG */
254 create_unimplemented_device("microchip.pfsoc.sysreg",
255 memmap[MICROCHIP_PFSOC_SYSREG].base,
256 memmap[MICROCHIP_PFSOC_SYSREG].size);
257
258 /* MPUCFG */
259 create_unimplemented_device("microchip.pfsoc.mpucfg",
260 memmap[MICROCHIP_PFSOC_MPUCFG].base,
261 memmap[MICROCHIP_PFSOC_MPUCFG].size);
262
263 /* SDHCI */
264 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
266 memmap[MICROCHIP_PFSOC_EMMC_SD].base);
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
268 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
269
270 /* MMUARTs */
271 s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
272 memmap[MICROCHIP_PFSOC_MMUART0].base,
273 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
274 serial_hd(0));
275 s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
276 memmap[MICROCHIP_PFSOC_MMUART1].base,
277 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
278 serial_hd(1));
279 s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
280 memmap[MICROCHIP_PFSOC_MMUART2].base,
281 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
282 serial_hd(2));
283 s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
284 memmap[MICROCHIP_PFSOC_MMUART3].base,
285 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
286 serial_hd(3));
287 s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
288 memmap[MICROCHIP_PFSOC_MMUART4].base,
289 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
290 serial_hd(4));
291
292 /* GEMs */
293
294 nd = &nd_table[0];
295 if (nd->used) {
296 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
297 qdev_set_nic_properties(DEVICE(&s->gem0), nd);
298 }
299 nd = &nd_table[1];
300 if (nd->used) {
301 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
302 qdev_set_nic_properties(DEVICE(&s->gem1), nd);
303 }
304
305 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
306 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
307 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
308 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
309 memmap[MICROCHIP_PFSOC_GEM0].base);
310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
311 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
312
313 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
314 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
315 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
317 memmap[MICROCHIP_PFSOC_GEM1].base);
318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
319 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
320
321 /* GPIOs */
322 create_unimplemented_device("microchip.pfsoc.gpio0",
323 memmap[MICROCHIP_PFSOC_GPIO0].base,
324 memmap[MICROCHIP_PFSOC_GPIO0].size);
325 create_unimplemented_device("microchip.pfsoc.gpio1",
326 memmap[MICROCHIP_PFSOC_GPIO1].base,
327 memmap[MICROCHIP_PFSOC_GPIO1].size);
328 create_unimplemented_device("microchip.pfsoc.gpio2",
329 memmap[MICROCHIP_PFSOC_GPIO2].base,
330 memmap[MICROCHIP_PFSOC_GPIO2].size);
331
332 /* eNVM */
333 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
334 memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
335 &error_fatal);
336 memory_region_add_subregion(system_memory,
337 memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
338 envm_data);
339
340 /* IOSCBCFG */
341 create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
342 memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
343 memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
344 }
345
346 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
347 {
348 DeviceClass *dc = DEVICE_CLASS(oc);
349
350 dc->realize = microchip_pfsoc_soc_realize;
351 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
352 dc->user_creatable = false;
353 }
354
355 static const TypeInfo microchip_pfsoc_soc_type_info = {
356 .name = TYPE_MICROCHIP_PFSOC,
357 .parent = TYPE_DEVICE,
358 .instance_size = sizeof(MicrochipPFSoCState),
359 .instance_init = microchip_pfsoc_soc_instance_init,
360 .class_init = microchip_pfsoc_soc_class_init,
361 };
362
363 static void microchip_pfsoc_soc_register_types(void)
364 {
365 type_register_static(&microchip_pfsoc_soc_type_info);
366 }
367
368 type_init(microchip_pfsoc_soc_register_types)
369
370 static void microchip_icicle_kit_machine_init(MachineState *machine)
371 {
372 MachineClass *mc = MACHINE_GET_CLASS(machine);
373 const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
374 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
375 MemoryRegion *system_memory = get_system_memory();
376 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
377 DriveInfo *dinfo = drive_get_next(IF_SD);
378
379 /* Sanity check on RAM size */
380 if (machine->ram_size < mc->default_ram_size) {
381 char *sz = size_to_str(mc->default_ram_size);
382 error_report("Invalid RAM size, should be bigger than %s", sz);
383 g_free(sz);
384 exit(EXIT_FAILURE);
385 }
386
387 /* Initialize SoC */
388 object_initialize_child(OBJECT(machine), "soc", &s->soc,
389 TYPE_MICROCHIP_PFSOC);
390 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
391
392 /* Register RAM */
393 memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
394 machine->ram_size, &error_fatal);
395 memory_region_add_subregion(system_memory,
396 memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
397
398 /* Load the firmware */
399 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
400
401 /* Attach an SD card */
402 if (dinfo) {
403 CadenceSDHCIState *sdhci = &(s->soc.sdhci);
404 DeviceState *card = qdev_new(TYPE_SD_CARD);
405
406 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
407 &error_fatal);
408 qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
409 }
410 }
411
412 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
413 {
414 MachineClass *mc = MACHINE_CLASS(oc);
415
416 mc->desc = "Microchip PolarFire SoC Icicle Kit";
417 mc->init = microchip_icicle_kit_machine_init;
418 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
419 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
420 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
421 mc->default_cpus = mc->min_cpus;
422 mc->default_ram_size = 1 * GiB;
423 }
424
425 static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
426 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
427 .parent = TYPE_MACHINE,
428 .class_init = microchip_icicle_kit_machine_class_init,
429 .instance_size = sizeof(MicrochipIcicleKitState),
430 };
431
432 static void microchip_icicle_kit_machine_init_register_types(void)
433 {
434 type_register_static(&microchip_icicle_kit_machine_typeinfo);
435 }
436
437 type_init(microchip_icicle_kit_machine_init_register_types)
AR7 emulation for QEMU