| commit | 9eb8b14a70e57bc1449afc08aa4bf3131ee680d8 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Thu, 9 Jul 2020 10:05:43 +0000 (9 03:05 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 14 Jul 2020 00:25:37 +0000 (13 17:25 -0700) | ||
| tree | 90c929a77f1d618413f830bc4b8f9fb8005b8249 | treesnapshot (tar.gz zip) |
| parent | 8590f53661ec678fd3aa97b4da212b0c00056c2e | commitdiff |
hw/riscv: Modify MROM size to end at 0x10000
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| hw/riscv/spike.c | diffblobblamehistory | |
| hw/riscv/virt.c | diffblobblamehistory |