| commit | ecdfe393b69985eb90ac4921287439dc47ed35b4 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:20:06 +0000 (6 09:20 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:47 +0000 (17 08:42 -0700) | ||
| tree | 18e3169109e7b7dde7bea572a48d9335bf9949f9 | treesnapshot (tar.gz zip) |
| parent | f3d47d580402d11b73108de807031124c135e370 | commitdiff |
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |