| commit | af14c840418bee1b22e5b1bc403dcc8c69492517 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:20:10 +0000 (6 09:20 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:48 +0000 (17 08:42 -0700) | ||
| tree | 432e45bec6780943fc6095493ba1d829a6bde658 | treesnapshot (tar.gz zip) |
| parent | e1724d09a6dc090063cad9d88d9994b9f55f5716 | commitdiff |
riscv: sifive_u: Add PRCI block to the SoC
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |