| commit | 56449d20e937e807e4fc35fa3e5a38f7636e7046 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:19:58 +0000 (6 09:19 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:46 +0000 (17 08:42 -0700) | ||
| tree | 43aba52df5fbc31c9135873e04506163ddb773e8 | treesnapshot (tar.gz zip) |
| parent | 9baa9f7c9f651dfc7ee8a4abd46c4036f6841f64 | commitdiff |
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/Makefile.objs | diffblobblamehistory | |
| hw/riscv/sifive_e.c | diffblobblamehistory | |
| hw/riscv/sifive_e_prci.c | [moved from hw/riscv/sifive_prci.c with 51% similarity] | diffblobblamehistory |
| include/hw/riscv/sifive_e_prci.h | [new file with mode: 0644] | blob |
| include/hw/riscv/sifive_prci.h | [deleted file] | blobblamehistory |