| commit | 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Tue, 1 Sep 2020 01:38:58 +0000 (1 09:38 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 9 Sep 2020 22:54:18 +0000 (9 15:54 -0700) | ||
| tree | b8e8f5ca6ba769ca3ac776411be5f2d75d72781b | treesnapshot (tar.gz zip) |
| parent | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 | commitdiff |
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/opentitan.c | diffblobblamehistory | |
| hw/riscv/sifive_e.c | diffblobblamehistory | |
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| target/riscv/cpu.c | diffblobblamehistory |