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target/riscv: cpu: Set reset vector based on the configured property value
[qemu/ar7.git] / hw / riscv / sifive_u.c
blob404d5e6918338653c4692b8df5236bde4b96f126
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 *
18 * This board currently generates devicetree dynamically that indicates at least
19 * two harts and up to five harts.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms and conditions of the GNU General Public License,
23 * version 2 or later, as published by the Free Software Foundation.
24 *
25 * This program is distributed in the hope it will be useful, but WITHOUT
26 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
27 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
28 * more details.
29 *
30 * You should have received a copy of the GNU General Public License along with
31 * this program. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34 #include "qemu/osdep.h"
35 #include "qemu/log.h"
36 #include "qemu/error-report.h"
37 #include "qapi/error.h"
38 #include "qapi/visitor.h"
39 #include "hw/boards.h"
40 #include "hw/irq.h"
41 #include "hw/loader.h"
42 #include "hw/sysbus.h"
43 #include "hw/char/serial.h"
44 #include "hw/cpu/cluster.h"
45 #include "hw/misc/unimp.h"
46 #include "target/riscv/cpu.h"
47 #include "hw/riscv/riscv_hart.h"
48 #include "hw/riscv/sifive_plic.h"
49 #include "hw/riscv/sifive_clint.h"
50 #include "hw/riscv/sifive_uart.h"
51 #include "hw/riscv/sifive_u.h"
52 #include "hw/riscv/boot.h"
53 #include "chardev/char.h"
54 #include "net/eth.h"
55 #include "sysemu/arch_init.h"
56 #include "sysemu/device_tree.h"
57 #include "sysemu/runstate.h"
58 #include "sysemu/sysemu.h"
59
60 #include <libfdt.h>
61
62 #if defined(TARGET_RISCV32)
63 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
64 #else
65 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin"
66 #endif
67
68 static const struct MemmapEntry {
69 hwaddr base;
70 hwaddr size;
71 } sifive_u_memmap[] = {
72 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
73 [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
74 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
75 [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
76 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
77 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
78 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
79 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
80 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
81 [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
82 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
83 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
84 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
85 [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
86 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
87 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
88 };
89
90 #define OTP_SERIAL 1
91 #define GEM_REVISION 0x10070109
92
93 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
94 uint64_t mem_size, const char *cmdline)
95 {
96 MachineState *ms = MACHINE(qdev_get_machine());
97 void *fdt;
98 int cpu;
99 uint32_t *cells;
100 char *nodename;
101 char ethclk_names[] = "pclk\0hclk";
102 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
103 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
104
105 fdt = s->fdt = create_device_tree(&s->fdt_size);
106 if (!fdt) {
107 error_report("create_device_tree() failed");
108 exit(1);
109 }
110
111 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
112 qemu_fdt_setprop_string(fdt, "/", "compatible",
113 "sifive,hifive-unleashed-a00");
114 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
115 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
116
117 qemu_fdt_add_subnode(fdt, "/soc");
118 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
119 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
120 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
121 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
122
123 hfclk_phandle = phandle++;
124 nodename = g_strdup_printf("/hfclk");
125 qemu_fdt_add_subnode(fdt, nodename);
126 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
127 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
128 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
129 SIFIVE_U_HFCLK_FREQ);
130 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
131 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
132 g_free(nodename);
133
134 rtcclk_phandle = phandle++;
135 nodename = g_strdup_printf("/rtcclk");
136 qemu_fdt_add_subnode(fdt, nodename);
137 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
138 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
139 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
140 SIFIVE_U_RTCCLK_FREQ);
141 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
142 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
143 g_free(nodename);
144
145 nodename = g_strdup_printf("/memory@%lx",
146 (long)memmap[SIFIVE_U_DRAM].base);
147 qemu_fdt_add_subnode(fdt, nodename);
148 qemu_fdt_setprop_cells(fdt, nodename, "reg",
149 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
150 mem_size >> 32, mem_size);
151 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
152 g_free(nodename);
153
154 qemu_fdt_add_subnode(fdt, "/cpus");
155 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
156 SIFIVE_CLINT_TIMEBASE_FREQ);
157 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
158 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
159
160 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
161 int cpu_phandle = phandle++;
162 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
163 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
164 char *isa;
165 qemu_fdt_add_subnode(fdt, nodename);
166 /* cpu 0 is the management hart that does not have mmu */
167 if (cpu != 0) {
168 #if defined(TARGET_RISCV32)
169 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
170 #else
171 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
172 #endif
173 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
174 } else {
175 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
176 }
177 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
178 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
179 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
180 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
181 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
182 qemu_fdt_add_subnode(fdt, intc);
183 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
184 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
185 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
186 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
187 g_free(isa);
188 g_free(intc);
189 g_free(nodename);
190 }
191
192 cells = g_new0(uint32_t, ms->smp.cpus * 4);
193 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
194 nodename =
195 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
196 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
197 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
198 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
199 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
200 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
201 g_free(nodename);
202 }
203 nodename = g_strdup_printf("/soc/clint@%lx",
204 (long)memmap[SIFIVE_U_CLINT].base);
205 qemu_fdt_add_subnode(fdt, nodename);
206 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
207 qemu_fdt_setprop_cells(fdt, nodename, "reg",
208 0x0, memmap[SIFIVE_U_CLINT].base,
209 0x0, memmap[SIFIVE_U_CLINT].size);
210 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
211 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
212 g_free(cells);
213 g_free(nodename);
214
215 nodename = g_strdup_printf("/soc/otp@%lx",
216 (long)memmap[SIFIVE_U_OTP].base);
217 qemu_fdt_add_subnode(fdt, nodename);
218 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
219 qemu_fdt_setprop_cells(fdt, nodename, "reg",
220 0x0, memmap[SIFIVE_U_OTP].base,
221 0x0, memmap[SIFIVE_U_OTP].size);
222 qemu_fdt_setprop_string(fdt, nodename, "compatible",
223 "sifive,fu540-c000-otp");
224 g_free(nodename);
225
226 prci_phandle = phandle++;
227 nodename = g_strdup_printf("/soc/clock-controller@%lx",
228 (long)memmap[SIFIVE_U_PRCI].base);
229 qemu_fdt_add_subnode(fdt, nodename);
230 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
231 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
232 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
233 hfclk_phandle, rtcclk_phandle);
234 qemu_fdt_setprop_cells(fdt, nodename, "reg",
235 0x0, memmap[SIFIVE_U_PRCI].base,
236 0x0, memmap[SIFIVE_U_PRCI].size);
237 qemu_fdt_setprop_string(fdt, nodename, "compatible",
238 "sifive,fu540-c000-prci");
239 g_free(nodename);
240
241 plic_phandle = phandle++;
242 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
243 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
244 nodename =
245 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
246 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
247 /* cpu 0 is the management hart that does not have S-mode */
248 if (cpu == 0) {
249 cells[0] = cpu_to_be32(intc_phandle);
250 cells[1] = cpu_to_be32(IRQ_M_EXT);
251 } else {
252 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
253 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
254 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
255 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
256 }
257 g_free(nodename);
258 }
259 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
260 (long)memmap[SIFIVE_U_PLIC].base);
261 qemu_fdt_add_subnode(fdt, nodename);
262 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
263 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
264 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
265 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
266 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
267 qemu_fdt_setprop_cells(fdt, nodename, "reg",
268 0x0, memmap[SIFIVE_U_PLIC].base,
269 0x0, memmap[SIFIVE_U_PLIC].size);
270 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
271 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
272 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
273 g_free(cells);
274 g_free(nodename);
275
276 gpio_phandle = phandle++;
277 nodename = g_strdup_printf("/soc/gpio@%lx",
278 (long)memmap[SIFIVE_U_GPIO].base);
279 qemu_fdt_add_subnode(fdt, nodename);
280 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
281 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
282 prci_phandle, PRCI_CLK_TLCLK);
283 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
284 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
285 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
286 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
287 qemu_fdt_setprop_cells(fdt, nodename, "reg",
288 0x0, memmap[SIFIVE_U_GPIO].base,
289 0x0, memmap[SIFIVE_U_GPIO].size);
290 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
291 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
292 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
293 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
294 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
295 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
296 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
297 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
298 g_free(nodename);
299
300 nodename = g_strdup_printf("/gpio-restart");
301 qemu_fdt_add_subnode(fdt, nodename);
302 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
303 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
304 g_free(nodename);
305
306 nodename = g_strdup_printf("/soc/cache-controller@%lx",
307 (long)memmap[SIFIVE_U_L2CC].base);
308 qemu_fdt_add_subnode(fdt, nodename);
309 qemu_fdt_setprop_cells(fdt, nodename, "reg",
310 0x0, memmap[SIFIVE_U_L2CC].base,
311 0x0, memmap[SIFIVE_U_L2CC].size);
312 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
313 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
314 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
315 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
316 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
317 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
318 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
319 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
320 qemu_fdt_setprop_string(fdt, nodename, "compatible",
321 "sifive,fu540-c000-ccache");
322 g_free(nodename);
323
324 phy_phandle = phandle++;
325 nodename = g_strdup_printf("/soc/ethernet@%lx",
326 (long)memmap[SIFIVE_U_GEM].base);
327 qemu_fdt_add_subnode(fdt, nodename);
328 qemu_fdt_setprop_string(fdt, nodename, "compatible",
329 "sifive,fu540-c000-gem");
330 qemu_fdt_setprop_cells(fdt, nodename, "reg",
331 0x0, memmap[SIFIVE_U_GEM].base,
332 0x0, memmap[SIFIVE_U_GEM].size,
333 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
334 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
335 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
336 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
337 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
338 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
339 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
340 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
341 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
342 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
343 sizeof(ethclk_names));
344 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
345 s->soc.gem.conf.macaddr.a, ETH_ALEN);
346 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
347 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
348
349 qemu_fdt_add_subnode(fdt, "/aliases");
350 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
351
352 g_free(nodename);
353
354 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
355 (long)memmap[SIFIVE_U_GEM].base);
356 qemu_fdt_add_subnode(fdt, nodename);
357 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
358 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
359 g_free(nodename);
360
361 nodename = g_strdup_printf("/soc/serial@%lx",
362 (long)memmap[SIFIVE_U_UART0].base);
363 qemu_fdt_add_subnode(fdt, nodename);
364 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
365 qemu_fdt_setprop_cells(fdt, nodename, "reg",
366 0x0, memmap[SIFIVE_U_UART0].base,
367 0x0, memmap[SIFIVE_U_UART0].size);
368 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
369 prci_phandle, PRCI_CLK_TLCLK);
370 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
371 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
372
373 qemu_fdt_add_subnode(fdt, "/chosen");
374 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
375 if (cmdline) {
376 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
377 }
378
379 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
380
381 g_free(nodename);
382 }
383
384 static void sifive_u_machine_reset(void *opaque, int n, int level)
385 {
386 /* gpio pin active low triggers reset */
387 if (!level) {
388 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
389 }
390 }
391
392 static void sifive_u_machine_init(MachineState *machine)
393 {
394 const struct MemmapEntry *memmap = sifive_u_memmap;
395 SiFiveUState *s = RISCV_U_MACHINE(machine);
396 MemoryRegion *system_memory = get_system_memory();
397 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
398 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
399 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
400 uint32_t start_addr_hi32 = 0x00000000;
401 int i;
402 uint32_t fdt_load_addr;
403 uint64_t kernel_entry;
404
405 /* Initialize SoC */
406 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
407 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
408 &error_abort);
409 qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
410
411 /* register RAM */
412 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
413 machine->ram_size, &error_fatal);
414 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
415 main_mem);
416
417 /* register QSPI0 Flash */
418 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
419 memmap[SIFIVE_U_FLASH0].size, &error_fatal);
420 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
421 flash0);
422
423 /* register gpio-restart */
424 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
425 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
426
427 /* create device tree */
428 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
429
430 if (s->start_in_flash) {
431 /*
432 * If start_in_flash property is given, assign s->msel to a value
433 * that representing booting from QSPI0 memory-mapped flash.
434 *
435 * This also means that when both start_in_flash and msel properties
436 * are given, start_in_flash takes the precedence over msel.
437 *
438 * Note this is to keep backward compatibility not to break existing
439 * users that use start_in_flash property.
440 */
441 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
442 }
443
444 switch (s->msel) {
445 case MSEL_MEMMAP_QSPI0_FLASH:
446 start_addr = memmap[SIFIVE_U_FLASH0].base;
447 break;
448 case MSEL_L2LIM_QSPI0_FLASH:
449 case MSEL_L2LIM_QSPI2_SD:
450 start_addr = memmap[SIFIVE_U_L2LIM].base;
451 break;
452 default:
453 start_addr = memmap[SIFIVE_U_DRAM].base;
454 break;
455 }
456
457 riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
458
459 if (machine->kernel_filename) {
460 kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
461
462 if (machine->initrd_filename) {
463 hwaddr start;
464 hwaddr end = riscv_load_initrd(machine->initrd_filename,
465 machine->ram_size, kernel_entry,
466 &start);
467 qemu_fdt_setprop_cell(s->fdt, "/chosen",
468 "linux,initrd-start", start);
469 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
470 end);
471 }
472 } else {
473 /*
474 * If dynamic firmware is used, it doesn't know where is the next mode
475 * if kernel argument is not set.
476 */
477 kernel_entry = 0;
478 }
479
480 /* Compute the fdt load address in dram */
481 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
482 machine->ram_size, s->fdt);
483 #if defined(TARGET_RISCV64)
484 start_addr_hi32 = start_addr >> 32;
485 #endif
486
487 /* reset vector */
488 uint32_t reset_vec[11] = {
489 s->msel, /* MSEL pin state */
490 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
491 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
492 0xf1402573, /* csrr a0, mhartid */
493 #if defined(TARGET_RISCV32)
494 0x0202a583, /* lw a1, 32(t0) */
495 0x0182a283, /* lw t0, 24(t0) */
496 #elif defined(TARGET_RISCV64)
497 0x0202b583, /* ld a1, 32(t0) */
498 0x0182b283, /* ld t0, 24(t0) */
499 #endif
500 0x00028067, /* jr t0 */
501 start_addr, /* start: .dword */
502 start_addr_hi32,
503 fdt_load_addr, /* fdt_laddr: .dword */
504 0x00000000,
505 /* fw_dyn: */
506 };
507
508 /* copy in the reset vector in little_endian byte order */
509 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
510 reset_vec[i] = cpu_to_le32(reset_vec[i]);
511 }
512 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
513 memmap[SIFIVE_U_MROM].base, &address_space_memory);
514
515 riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
516 memmap[SIFIVE_U_MROM].size,
517 sizeof(reset_vec), kernel_entry);
518 }
519
520 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
521 {
522 SiFiveUState *s = RISCV_U_MACHINE(obj);
523
524 return s->start_in_flash;
525 }
526
527 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
528 {
529 SiFiveUState *s = RISCV_U_MACHINE(obj);
530
531 s->start_in_flash = value;
532 }
533
534 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
535 const char *name, void *opaque,
536 Error **errp)
537 {
538 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
539 }
540
541 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
542 const char *name, void *opaque,
543 Error **errp)
544 {
545 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
546 }
547
548 static void sifive_u_machine_instance_init(Object *obj)
549 {
550 SiFiveUState *s = RISCV_U_MACHINE(obj);
551
552 s->start_in_flash = false;
553 object_property_add_bool(obj, "start-in-flash",
554 sifive_u_machine_get_start_in_flash,
555 sifive_u_machine_set_start_in_flash);
556 object_property_set_description(obj, "start-in-flash",
557 "Set on to tell QEMU's ROM to jump to "
558 "flash. Otherwise QEMU will jump to DRAM "
559 "or L2LIM depending on the msel value");
560
561 s->msel = 0;
562 object_property_add(obj, "msel", "uint32",
563 sifive_u_machine_get_uint32_prop,
564 sifive_u_machine_set_uint32_prop, NULL, &s->msel);
565 object_property_set_description(obj, "msel",
566 "Mode Select (MSEL[3:0]) pin state");
567
568 s->serial = OTP_SERIAL;
569 object_property_add(obj, "serial", "uint32",
570 sifive_u_machine_get_uint32_prop,
571 sifive_u_machine_set_uint32_prop, NULL, &s->serial);
572 object_property_set_description(obj, "serial", "Board serial number");
573 }
574
575 static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
576 {
577 MachineClass *mc = MACHINE_CLASS(oc);
578
579 mc->desc = "RISC-V Board compatible with SiFive U SDK";
580 mc->init = sifive_u_machine_init;
581 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
582 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
583 mc->default_cpus = mc->min_cpus;
584 }
585
586 static const TypeInfo sifive_u_machine_typeinfo = {
587 .name = MACHINE_TYPE_NAME("sifive_u"),
588 .parent = TYPE_MACHINE,
589 .class_init = sifive_u_machine_class_init,
590 .instance_init = sifive_u_machine_instance_init,
591 .instance_size = sizeof(SiFiveUState),
592 };
593
594 static void sifive_u_machine_init_register_types(void)
595 {
596 type_register_static(&sifive_u_machine_typeinfo);
597 }
598
599 type_init(sifive_u_machine_init_register_types)
600
601 static void sifive_u_soc_instance_init(Object *obj)
602 {
603 MachineState *ms = MACHINE(qdev_get_machine());
604 SiFiveUSoCState *s = RISCV_U_SOC(obj);
605
606 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
607 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
608
609 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
610 TYPE_RISCV_HART_ARRAY);
611 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
612 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
613 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
614 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
615
616 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
617 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
618
619 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
620 TYPE_RISCV_HART_ARRAY);
621 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
622 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
623 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
624 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
625
626 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
627 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
628 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
629 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
630 }
631
632 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
633 {
634 MachineState *ms = MACHINE(qdev_get_machine());
635 SiFiveUSoCState *s = RISCV_U_SOC(dev);
636 const struct MemmapEntry *memmap = sifive_u_memmap;
637 MemoryRegion *system_memory = get_system_memory();
638 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
639 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
640 char *plic_hart_config;
641 size_t plic_hart_config_len;
642 int i;
643 NICInfo *nd = &nd_table[0];
644
645 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
646 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
647 /*
648 * The cluster must be realized after the RISC-V hart array container,
649 * as the container's CPU object is only created on realize, and the
650 * CPU must exist and have been parented into the cluster before the
651 * cluster is realized.
652 */
653 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
654 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
655
656 /* boot rom */
657 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
658 memmap[SIFIVE_U_MROM].size, &error_fatal);
659 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
660 mask_rom);
661
662 /*
663 * Add L2-LIM at reset size.
664 * This should be reduced in size as the L2 Cache Controller WayEnable
665 * register is incremented. Unfortunately I don't see a nice (or any) way
666 * to handle reducing or blocking out the L2 LIM while still allowing it
667 * be re returned to all enabled after a reset. For the time being, just
668 * leave it enabled all the time. This won't break anything, but will be
669 * too generous to misbehaving guests.
670 */
671 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
672 memmap[SIFIVE_U_L2LIM].size, &error_fatal);
673 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
674 l2lim_mem);
675
676 /* create PLIC hart topology configuration string */
677 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
678 ms->smp.cpus;
679 plic_hart_config = g_malloc0(plic_hart_config_len);
680 for (i = 0; i < ms->smp.cpus; i++) {
681 if (i != 0) {
682 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
683 plic_hart_config_len);
684 } else {
685 strncat(plic_hart_config, "M", plic_hart_config_len);
686 }
687 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
688 }
689
690 /* MMIO */
691 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
692 plic_hart_config, 0,
693 SIFIVE_U_PLIC_NUM_SOURCES,
694 SIFIVE_U_PLIC_NUM_PRIORITIES,
695 SIFIVE_U_PLIC_PRIORITY_BASE,
696 SIFIVE_U_PLIC_PENDING_BASE,
697 SIFIVE_U_PLIC_ENABLE_BASE,
698 SIFIVE_U_PLIC_ENABLE_STRIDE,
699 SIFIVE_U_PLIC_CONTEXT_BASE,
700 SIFIVE_U_PLIC_CONTEXT_STRIDE,
701 memmap[SIFIVE_U_PLIC].size);
702 g_free(plic_hart_config);
703 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
704 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
705 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
706 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
707 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
708 memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
709 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
710
711 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
712 return;
713 }
714 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
715
716 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
717 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
718 return;
719 }
720 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
721
722 /* Pass all GPIOs to the SOC layer so they are available to the board */
723 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
724
725 /* Connect GPIO interrupts to the PLIC */
726 for (i = 0; i < 16; i++) {
727 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
728 qdev_get_gpio_in(DEVICE(s->plic),
729 SIFIVE_U_GPIO_IRQ0 + i));
730 }
731
732 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
733 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
734 return;
735 }
736 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
737
738 /* FIXME use qdev NIC properties instead of nd_table[] */
739 if (nd->used) {
740 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
741 qdev_set_nic_properties(DEVICE(&s->gem), nd);
742 }
743 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
744 &error_abort);
745 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
746 return;
747 }
748 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
749 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
750 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
751
752 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
753 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
754
755 create_unimplemented_device("riscv.sifive.u.dmc",
756 memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
757
758 create_unimplemented_device("riscv.sifive.u.l2cc",
759 memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
760 }
761
762 static Property sifive_u_soc_props[] = {
763 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
764 DEFINE_PROP_END_OF_LIST()
765 };
766
767 static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
768 {
769 DeviceClass *dc = DEVICE_CLASS(oc);
770
771 device_class_set_props(dc, sifive_u_soc_props);
772 dc->realize = sifive_u_soc_realize;
773 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
774 dc->user_creatable = false;
775 }
776
777 static const TypeInfo sifive_u_soc_type_info = {
778 .name = TYPE_RISCV_U_SOC,
779 .parent = TYPE_DEVICE,
780 .instance_size = sizeof(SiFiveUSoCState),
781 .instance_init = sifive_u_soc_instance_init,
782 .class_init = sifive_u_soc_class_init,
783 };
784
785 static void sifive_u_soc_register_types(void)
786 {
787 type_register_static(&sifive_u_soc_type_info);
788 }
789
790 type_init(sifive_u_soc_register_types)
AR7 emulation for QEMU