| commit | 6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Mon, 20 Jul 2020 06:49:08 +0000 (19 23:49 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Sat, 22 Aug 2020 05:37:55 +0000 (21 22:37 -0700) | ||
| tree | 7d6cd382e30b252392db16e2ce1ba9fd60e51b50 | treesnapshot (tar.gz zip) |
| parent | ec80f8745931f0c8f8f2251e16bcc69170cf6f27 | commitdiff |
hw/riscv: sifive_u: Add a dummy L2 cache controller device
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |