| commit | 4b55bc2b5f7ff065da5d2b813ee5153c598d3764 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Fri, 6 Sep 2019 16:20:12 +0000 (6 09:20 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 17 Sep 2019 15:42:48 +0000 (17 08:42 -0700) | ||
| tree | 8ed72442f9af80bb4b86e3add122d84f811f3bd3 | treesnapshot (tar.gz zip) |
| parent | 806c64b7b0e782b7f1414478486c67df718a0f00 | commitdiff |
riscv: sifive_u: Update UART base addresses and IRQs
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jonathan Behrens <fintelia@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jonathan Behrens <fintelia@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |