hw/riscv: sifive_e: Correct debug block size
commite79d27cb322b60b460b709d2c74ff7d77cde0565
authorBin Meng <bmeng.cn@gmail.com>
Thu, 16 Jul 2020 09:30:56 +0000 (16 02:30 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 22 Jul 2020 16:39:46 +0000 (22 09:39 -0700)
tree68cd5478640ed930427eba0646e3bf19b1093e50
parent3e09396e36dff4234afd6f6fd51861949be383e1
hw/riscv: sifive_e: Correct debug block size

Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:

  FE310-G000: 0x100 - 0xFFF
  FE310-G002: 0x0   - 0xFFF

Change the size to 0x1000 that applies to both.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/sifive_e.c