| commit | 3e09396e36dff4234afd6f6fd51861949be383e1 | |
| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | |
| Tue, 21 Jul 2020 13:37:42 +0000 (21 21:37 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 22 Jul 2020 16:39:46 +0000 (22 09:39 -0700) | ||
| tree | 85b2f145299fedaff790c06c74445c6d020003fb | treesnapshot (tar.gz zip) |
| parent | eabfeb0cb9e054108b3e29a3a85363b3d80d9c38 | commitdiff |
target/riscv: fix vector index load/store constraints
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/insn_trans/trans_rvv.inc.c | diffblobblamehistory |