| commit | c696e1f2b392af19653e82da26df3c61b85ab5a2 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Tue, 1 Sep 2020 01:39:02 +0000 (1 09:39 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 9 Sep 2020 22:54:18 +0000 (9 15:54 -0700) | ||
| tree | 1fd7a96bbc40a5bf5aae06f7de551b684876c443 | treesnapshot (tar.gz zip) |
| parent | 8f2ac39d5d307589faca1d00d55a1a8054d53b0e | commitdiff |
hw/sd: Add Cadence SDHCI emulation
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/sd/Kconfig | diffblobblamehistory | |
| hw/sd/cadence_sdhci.c | [new file with mode: 0644] | blob |
| hw/sd/meson.build | diffblobblamehistory | |
| include/hw/sd/cadence_sdhci.h | [new file with mode: 0644] | blob |