repo.or.cz
/
qemu
/
ar7.git
/
search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
first
·
prev
·
next
hw/intc: Move sifive_plic.h to the include directory
2020-10-22
Bi
n
Me
n
g
hw/intc: Move sifiv
e
_plic
.
h to th
e
i
nclude direc
t
ory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Sort the Kconfig
o
ptions in a
l
phabetical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv:
D
r
op CONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ri
s
c
v
: Alwa
y
s
bu
i
ld r
i
scv_
h
art
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv: M
o
ve sifive_t
e
st model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifi
v
e_uart m
o
de
l
to h
w
/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/risc
v
: Move riscv_
h
tif model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifi
v
e_pl
i
c model
t
o hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/r
i
sc
v
: Move sifi
v
e_clint mo
d
el
t
o
hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
isc
v
: Move sifive_gpio model
t
o hw/
g
p
i
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
hw/riscv: Move sifive_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
Move si
f
ive_u_prci mod
e
l to hw
/
mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv:
M
ove sifive_e
_
prci mod
e
l t
o
hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/risc
v
:
sifive_u: Co
n
nect a DMA
c
ontroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: cli
n
t: Avoid using hard-coded timebase freq
u
ency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
h
w/riscv: microchip_
p
fsoc: H
o
o
k
GPIO con
t
rollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: microch
i
p_
p
fsoc: Connect 2
Ca
d
e
nce GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
hw/arm: xlnx: Set all
boards' GEM
'phy-addr' pro
p
erty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
e
ng
hw/
n
e
t
: caden
c
e_gem: Add
a
new 'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
h
w/r
i
scv: m
i
crochi
p
_pfsoc
:
Conn
e
ct a
DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: Ad
d
Si
F
ive pl
a
tfo
r
m
D
MA cont
r
oller
e
m
u
la
t
ion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
micro
c
hip_pfsoc: Connect
a
C
a
dence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/sd: Add Cadence SDHCI em
u
latio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: mi
c
rochip_
p
fsoc: Conne
c
t
5
MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ch
a
r
: Add Microchip
P
ol
a
rF
i
r
e SoC MMUART
emulatio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/r
i
sc
v
: Initial suppor
t
for Mi
c
rochip PolarFir
e
SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
target/riscv: cpu: Set reset vector based on the
c
onfigured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: hart: Add a ne
w
'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in
Meng
ta
r
get/riscv: cp
u
: Add a ne
w
'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
gitlab-ci/o
p
ensbi: Update GitLa
b
CI to build generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/riscv: spike: Change the defau
l
t bio
s
to use gen
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/ri
s
cv: Use pre-bui
l
t bio
s
i
m
a
ge of generic platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
roms/Makefile: Build the ge
n
eric plat
f
or
m
for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
r
o
ms/o
p
e
n
sbi:
Up
g
rade from v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
ng
config
u
re:
C
r
e
a
te symbolic links for pc-bios/*
.
e
lf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifi
v
e
_
u
: Ad
d
a dummy
L2 cach
e
contro
l
ler
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Me
n
g
hw/sd: Corr
e
ct the maximu
m
s
ize of a Standard Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin M
e
ng
h
w
/sd: Fix i
n
correct
p
opu
l
a
ted functi
o
n sw
i
tch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin
Meng
hw/riscv:
si
f
ive
_
e:
C
o
rre
c
t debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
e
ng
h
w/riscv:
M
odi
f
y
MROM
s
ize
to e
n
d
a
t
0
x
10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Me
n
g
hw/riscv: virt: Sort
t
he
SoC
m
emmap table
e
ntri
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
MAINT
A
INERS:
Add a
n
entry fo
r
OpenSB
I
firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/ris
c
v: sifi
v
e_u: Add a dummy DDR m
e
mory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
ve_u: S
o
rt t
h
e So
C
memmap ta
b
le entri
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
M
eng
h
w
/riscv: sifive_u: S
u
pp
o
rt di
f
ferent
b
o
o
t
source
p
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/riscv: sifive: Ch
a
nge SiFive E/U CPU reset v
e
ct
o
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
t
a
rget/riscv: R
e
name IBEX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/
r
isc
v
: s
i
five_u: Add a new pr
o
perty msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
sifive_u: Rename ser
i
al pro
p
erty
g
et/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
hw/
r
i
s
cv: sifive_u: Add reset functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v
:
si
f
i
v
e_gp
i
o:
Do no
t
bl
i
ndly t
r
igger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
f
i
ve_u: Hook a GPIO
c
o
n
t
r
o
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: si
f
i
ve
_
gpio
:
Add a new 'ngp
i
o' prope
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Me
n
g
hw
/
riscv: sifive_gpio: Cle
a
n up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: s
i
f
i
ve_u: Generate device tree node for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive
_
u:
Simplify t
h
e
G
EM IR
Q
connec
t
code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
h
w/
r
i
s
cv: opentitan: Remove the ri
s
cv_ pr
e
fix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifi
v
e_e: Remove th
e
riscv_ pre
f
i
x of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
risc
v
: Keep the CPU init rou
t
ine names consisten
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
ris
c
v: Gen
e
ralize CPU init routine
f
or the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ri
s
cv: G
e
neralize CPU init r
o
utine for the gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
riscv: Generalize C
P
U init ro
u
tine f
o
r the base
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Me
n
g
h
w
/risc
v
: virt: Remove the riscv_ prefix of the mac
h
ine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/riscv:
s
ifive_u: Remove t
h
e
riscv_ prefix
o
f t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
r
i
scv: Chang
e
the default
b
ehavior
if no -b
i
os option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv
:
S
up
p
ress
t
he error report f
o
r
QEMU testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
rom
s
:
o
pensbi: Up
g
rad
e
fr
o
m v0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
i
n M
e
ng
hw/riscv: G
e
nerate corre
c
t "mm
u
-type" for 32-
b
it machi
n
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bi
n
Men
g
r
iscv/sifive_u
:
Add a serial p
r
ope
r
ty to
t
h
e
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
M
eng
gitlab-ci
.
y
m
l
:
Add jobs t
o
build
OpenSBI firmware bi
n
ar
i
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
riscv
:
s
ifive_u
:
Upd
a
te BI
O
S_FIL
E
NAME for 32-b
i
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bi
n
Meng
roms: opensbi: Add 32-bit fi
r
mw
a
re image for sifive_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms: opens
b
i
: Up
g
rade f
r
om v0
.
5
t
o
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Me
n
g
hw: ne
t
: ca
d
enc
e
_gem: Fix build
e
rrors in D
B
_PRI
N
T()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: virt: Allow
P
CI ad
d
ress
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: s
i
five_u
:
Add ethe
r
net0 t
o
the aliase
s
n
ode
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: hw: Drop "clock-freq
u
ency" pr
o
perty of cpu
n
odes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
ri
s
cv: S
k
ip ch
e
c
king CS
R
privilege level in debugg
e
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: sifive_u: Update model
and
c
o
m
pati
b
le strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
riscv: sif
i
v
e
_u: Remov
e
handcrafted clock nodes
for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Men
g
ri
s
cv: sifive_u:
F
ix broken GEM suppor
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
r
is
c
v: sifive_u: In
s
tantiate OTP
me
m
ory
w
ith
a ser
i
al
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: sif
i
ve: Impl
e
m
e
nt a mo
d
el
for SiFive FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: roms: Updat
e
defaul
t
b
ios for sif
i
ve_u
mac
h
in
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive_u: Change U
A
RT
node nam
e
in device tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
r
i
s
c
v: sifive_u
:
Up
d
ate UART
ba
s
e
a
ddresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u:
Referenc
e
PRCI c
l
ocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
r
i
scv: sifive_
u
: Add PRCI bl
o
c
k
t
o
the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: sifive_u: Gene
r
ate
h
fclk an
d
rtcclk no
d
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sifive
:
Imple
m
ent PRCI
model f
o
r FU
5
40
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
n
g
riscv
:
s
i
f
i
v
e_u: Update P
L
IC
ha
r
t to
p
ology conf
i
guration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv
:
sifive_u: Update
h
a
rt co
n
fig
u
ration to refle
c
t
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Set
t
h
e
m
inimum nu
m
ber of cpus
t
o 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: hart: Add a "har
t
i
d-bas
e
" p
r
operty to RISC
-
V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Meng
r
i
scv: hart:
Ext
r
a
c
t hart realize to a separate routine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: Add
a
sifiv
e
_cpu
.
h to include both E
and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: sifive_e:
D
rop sifive_mmio
_
e
m
ulate()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
risc
v
:
s
i
f
i
ve_e:
p
r
c
i
: Update the PRCI
registe
r
block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv:
s
ifive
_
e
:
p
rci:
Fix a t
y
po of hf
x
osc
c
fg register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
si
f
i
v
e: Re
n
a
me sifive
_
prci
.
{c, h} to sifive_e_
p
rci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
next