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hw/sd/sdhci: Document the datasheet used
2020-09-09
Bin Meng
hw/riscv: Sort the Kconfig
o
ptions in
a
lpha
b
etical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
en
g
hw/riscv: Drop CONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Always b
u
ild ri
s
cv
_
hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv
:
Move sifi
v
e_test mo
d
el
t
o hw
/
mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifive_ua
r
t model t
o
h
w
/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: Move riscv_
h
tif
m
odel to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
Move
s
i
f
ive
_
plic
model to hw/
i
ntc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: Mo
v
e
sifi
v
e_
c
lin
t
model to hw
/
intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: Move si
f
ive_gp
i
o
model to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: Move
s
ifive_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: Move sifive_u_prci model t
o
h
w
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Move sifive_e
_
pr
c
i
model to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/ri
s
cv: si
f
ive_u: Con
n
e
c
t
a DMA c
o
n
t
r
o
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Me
n
g
hw/ri
s
c
v
:
clint: Avoi
d
u
si
n
g hard-co
d
ed
t
i
mebase f
r
equency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw
/
riscv:
m
i
crochip_pfsoc:
H
ook GPIO contr
o
llers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: mic
r
ochip_pfsoc: Co
n
n
ect 2
Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/arm:
x
lnx: Set all boar
d
s' GEM 'ph
y
-addr'
p
r
ope
r
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/n
e
t
:
cadence_gem: A
d
d a new 'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: mic
r
ochip_pfso
c
: C
o
nnect a D
M
A controll
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w/dma: Add
SiFive platform DMA con
t
roller
e
m
ula
t
ion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
h
w/riscv:
m
icrochip_pfs
o
c:
Connect a C
a
de
n
ce SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd
:
Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv
:
mi
c
rochip_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
h
w
/char: Add Microchip PolarFire So
C
MMUART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv
:
In
i
tial sup
p
ort for Mic
r
ochip PolarFir
e
SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
tar
g
et/riscv: cpu
:
Set rese
t
vector based
o
n the configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: hart: Add a new '
r
e
setvec'
proper
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
e
n
g
target/riscv:
c
p
u: Add
a new
'
resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
ng
gitlab-ci/opensbi: Update GitL
a
b CI
t
o build generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
hw/ris
c
v: s
p
ik
e
: Change the default bios to use generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
hw/r
i
scv
:
Use
p
re-bui
l
t
b
ios
imag
e
o
f
generic platfor
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
r
oms/
M
akefile: Build the generic platf
o
rm for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
ro
m
s/open
s
b
i
: Up
g
rade from v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
confi
g
ure: Create s
y
m
b
olic links
fo
r
p
c
-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
hw/riscv:
sifive_u: Add a d
u
mmy
L
2 cache
c
ontroll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
in Meng
hw/sd: Correct the max
i
mum
s
ize of a
Standard Capacit
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/
s
d: Fix
i
ncorrec
t
pop
u
l
a
ted
f
unction switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin
M
e
n
g
hw/
r
isc
v
:
sifive_e: Correct
debug block s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n
M
eng
hw/r
i
sc
v
: Modif
y
MROM size
t
o end at
0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv: virt: Sort the SoC me
m
ma
p
tab
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINT
A
INERS: Add
a
n entry for OpenSB
I
firm
w
are
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Add
a
dummy DDR memory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: sifive_u: Sort the SoC memmap ta
b
le entrie
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
hw/ris
c
v: sifive_u
:
S
u
pport different boot source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifi
v
e: Change SiFive E/U CPU r
e
se
t
vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target/
r
iscv: Rename IBEX CPU i
n
i
t
routi
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv
:
sifive_u: Add a
n
e
w
property m
s
el
for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Rename serial p
r
operty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_
u
: Add reset functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv:
s
if
i
ve_g
p
io: Do not
blindly trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/ri
s
c
v: sifive_u: Hoo
k
a GP
I
O controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw/riscv: sifi
v
e_gpio: Add a ne
w
'
ngpio
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/ri
s
cv: sif
i
ve_gpio:
Clean up t
h
e codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u
:
Generate
d
evi
c
e tree node f
o
r OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
f
i
ve_u:
Simplify th
e
GEM IRQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: opentita
n
: Remov
e
the riscv_ p
r
efix of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
five_e: Re
m
ove the riscv_ pref
i
x of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv
:
Keep the CPU init routine nam
e
s
co
n
sis
t
ent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
riscv: Gener
a
lize CPU in
i
t r
o
u
t
ine for
t
he im
a
cu
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ri
s
c
v
: Generalize CPU init routine
for the
g
csu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
riscv: Generalize CPU in
i
t routine fo
r
the ba
s
e CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/
r
i
scv: vi
r
t
: Remove the riscv
_
prefix of the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Meng
hw/riscv: sifiv
e
_u: Re
m
ove the riscv_ p
r
e
f
ix
o
f
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
riscv: Change the default behav
i
or
if no -bios option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
ng
riscv: Sup
p
re
s
s the error rep
o
rt for Q
E
M
U testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
B
i
n Meng
r
o
ms
:
o
p
ens
b
i: Upgra
d
e from
v0
.
6 to v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/ri
s
cv: Gene
r
ate cor
r
ect "
m
m
u-type" for
3
2-bit m
a
chines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
in
Meng
riscv/sifive
_
u: Add a
s
erial pro
p
er
t
y
t
o
t
he sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Me
n
g
gitla
b
-ci
.
y
m
l
: Add jobs to bui
l
d OpenSBI
f
irmw
a
re bin
a
r
i
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
M
eng
r
i
scv:
s
ifive_
u
: U
p
d
at
e
BIO
S
_FILENAME
for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms: op
e
nsbi: Add 32
-
bit f
i
rmware
i
m
a
ge for sifiv
e
_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
ro
m
s:
op
e
nsbi: Upgrade from
v0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin M
e
n
g
hw: net: caden
c
e_gem: Fix build errors
in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin M
e
ng
riscv
:
virt: A
l
low P
C
I address
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bi
n
Meng
r
i
scv: si
f
ive_u: Add ethernet0 to the alia
s
e
s
node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: hw: Dr
o
p "clock-frequenc
y
" property of c
p
u
nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Men
g
ri
s
cv: Sk
i
p
c
he
c
k
i
ng C
S
R privilege
l
e
vel in debugg
e
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sifive
_
u: Update model and c
o
mpatible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Remo
v
e
handcrafted cl
o
ck no
d
es for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Fix broken
GEM
s
upport
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bi
n
Meng
riscv: sifive_
u
: Instantia
t
e OTP
memory
wi
t
h a s
e
rial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin
M
e
ng
ri
s
cv: sifive: Implemen
t
a mod
e
l for SiFive FU540
O
TP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: roms: Upd
a
te
defaul
t
bi
o
s for si
f
ive_u
m
ach
i
n
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: sifive_u:
C
hange
UART
node name in
d
evice tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin
Meng
riscv: sifiv
e
_u: Updat
e
UART base
add
r
esses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
B
in
Meng
riscv
:
sifiv
e
_
u: Ref
e
rence PR
C
I
clocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: sifive_u:
Add PRCI block t
o
the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv:
s
ifiv
e
_u: Ge
n
erate hf
c
lk
and rt
c
c
lk
n
odes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Men
g
risc
v
: sifive: Implement PR
C
I model
for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: sifive
_
u: U
p
da
t
e PLIC har
t
topolo
g
y co
n
figu
r
ation
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
r
i
sc
v
: sifi
v
e
_
u:
U
pdate hart configu
r
a
tion to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
B
i
n Meng
riscv: sifive_u: Set the
m
ini
m
um
number o
f
c
pus
to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Me
n
g
r
iscv:
ha
r
t
:
Add a "hartid
-
bas
e
" proper
t
y
to
RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv:
h
art: Extr
a
ct hart reali
z
e to
a se
p
arate
r
outine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
ri
s
cv: Add a sifive_cpu
.
h to in
c
l
ude both E and
U
cp
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin M
e
ng
riscv: si
f
ive_e:
Drop si
f
iv
e
_mmio_emulate()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Me
n
g
r
isc
v
: sifive
_
e: prci
:
Update the
P
RCI register block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: sif
i
v
e
_
e
: prci: Fix a
typo of hfxosccfg register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv: sifive: Rename
sifive_p
r
ci
.
{c, h
}
to si
f
iv
e
_e_prci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Men
g
riscv: sifive_u:
R
e
mo
v
e
t
he unne
c
essa
r
y
i
nc
l
ude of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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