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hw/intc/loongson: Fix incorrect 'core' calculation in liointc_read/write
2020-10-26
Bi
n
Men
g
hw/sd/sdcard: Zero out fun
c
tion se
l
ec
t
ion fields before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
hw
/
intc
:
Move
sifiv
e
_plic
.
h to
t
he in
c
lude directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Sort the Kcon
f
ig opt
i
ons i
n
alphab
e
tical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Drop CONFIG
_
SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Al
w
a
y
s
b
uild riscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/r
i
s
cv: Mo
v
e
si
f
ive_test
model to hw
/
m
i
sc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
e
ng
hw/riscv:
M
o
ve sifive_uart model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Move riscv_htif model
t
o hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move si
f
ive_plic model to hw/in
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sifive_
c
lint
m
odel to hw
/
int
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in
Meng
hw/
r
is
c
v: Move sifive_gp
i
o mo
d
el to hw
/
gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv:
Move
sifive_u_o
t
p mode
l
to
h
w
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: Move sifiv
e
_u
_
prci mode
l
to hw/
m
is
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mov
e
sifi
v
e_e
_
pr
c
i model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: sifive_
u
:
C
onne
c
t
a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv:
c
l
i
nt
:
Avoid usi
n
g h
a
r
d-c
o
de
d
timeba
s
e
fr
e
qu
e
ncy
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
ris
c
v
:
microchip_pfsoc: Hook GP
I
O c
o
ntrollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: microchip_
p
fsoc:
Connect
2
Cadence GEM
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
arm: xlnx: Set all b
o
ar
d
s' GEM 'phy-add
r
' proper
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
net: cadence_ge
m
:
A
dd a new
'
phy-addr
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: m
i
crochip_p
f
soc: Connect a DMA c
o
ntroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/dma:
Add SiFive platform DMA contro
l
ler emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
microchip_pfsoc: Conn
e
ct a Cadence
S
DHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/sd: Add Cadence SDHCI
e
mul
a
ti
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/
r
i
s
c
v
: microchip_p
f
soc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
c
h
a
r: Add
Mi
c
roch
i
p Po
l
arFire S
o
C MMUART
e
m
ulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
hw/risc
v
:
I
nitial supp
o
r
t for Microchip PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
targe
t
/risc
v
: cpu: Set reset vector b
a
sed on the con
f
igured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv:
hart: Add a new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
target/riscv: cpu
:
Add
a ne
w
'resetvec' prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-
c
i/o
p
ensbi: Upda
t
e GitLab CI to build generi
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
hw/riscv:
s
p
i
ke: Change the
default bios to use
gener
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/riscv: Use pre-built bi
o
s ima
g
e
o
f gene
r
i
c platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
n
g
roms/Makefile: Bu
i
ld the ge
n
eric platform for R
I
S
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi: Upgrade f
r
om v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
c
onfigure: Cre
a
te symbolic links for pc-
b
i
os/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifive_
u
: Add a dummy L2 ca
c
he controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin
Meng
h
w
/
sd: Corre
c
t
the m
a
xi
m
um si
z
e
o
f
a Standard Capac
i
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
en
g
hw/sd:
F
ix
i
ncorrect populated functio
n
switch statu
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/risc
v
:
sifive_e
:
Corr
e
ct debug block
s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
hw/r
i
sc
v
: Mo
d
ify MROM size to end at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw
/
riscv: virt: Sor
t
t
h
e SoC memma
p
t
a
ble entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
MAI
N
TA
I
NERS:
A
dd
an ent
r
y
for Op
e
nSBI
firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: si
f
iv
e
_u
:
Add a dummy D
D
R
memory
c
ontroller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: s
i
fiv
e
_u:
S
o
r
t the SoC memm
a
p
table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: s
i
five_
u
: Suppor
t
differ
e
nt boot sour
c
e per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv
:
s
ifive: Change SiFive E/U CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
t
ar
g
et/riscv
:
Renam
e
IB
E
X CPU init
r
ou
t
ine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
r
i
s
cv: sifiv
e
_u: A
d
d a new p
r
operty msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Men
g
hw/riscv: sifive_u: Re
n
ame serial property get/s
e
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
h
w/risc
v
: sifive_u: Add re
s
et fun
c
t
i
onal
i
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
ris
c
v
: sifive_gpio: Do
not bli
n
dly tri
g
ger
output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Hook a GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
hw/
r
i
s
cv:
s
ifive_
g
pio: A
d
d a new 'ngpio' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Clean up
the c
o
d
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw/riscv: sifive_u: Generate
d
ev
i
ce tree
n
o
de for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv
:
s
i
five_u: Simplify the GEM IRQ c
o
nnect cod
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: opentitan: Remove the ri
s
cv
_
prefix of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v:
s
if
i
ve_e
:
R
e
move the
ris
c
v_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
r
i
scv: Keep the CPU init rou
t
ine names consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
r
iscv: Gene
r
alize C
P
U i
n
i
t ro
u
tine for the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Men
g
riscv: G
e
neralize CPU init routine
f
or the gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
ris
c
v
:
Gener
a
li
z
e
CPU init routine
for the b
a
se CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Men
g
hw/riscv:
v
irt: Remov
e
the riscv_ pre
f
ix of the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/
r
iscv: sifive_u: Remove the riscv_ pre
f
ix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv: Cha
n
g
e
t
he
d
efa
u
lt behavior if no -bios
o
ption
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
ris
c
v: Suppress
th
e
error re
p
o
rt f
o
r
QE
M
U testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
B
in Meng
roms
:
opensb
i
: Up
g
rade from
v0
.
6
to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
in Meng
hw/ris
c
v: Generate c
o
rrect "
m
mu-type" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
r
isc
v
/si
f
ive_u: Add a s
e
rial property t
o
the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
in Men
g
gitlab
-
ci
.
yml: Add jobs to build
OpenSBI f
i
rm
w
a
r
e
b
ina
r
ies
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
risc
v
: sifive_
u
: Update BIOS_FILENAME fo
r
32
-
bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n Meng
r
o
ms:
opensbi:
Add 32-b
i
t fir
m
ware image
for sifi
v
e_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms: ope
n
sbi:
U
pgrade from v0
.
5 t
o
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Meng
h
w
:
n
et: cad
e
nce_ge
m
: Fix buil
d
errors in
D
B_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: virt: Allow PCI address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: sifive_u: Add e
t
h
e
rnet0 to the aliases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
risc
v
: hw:
D
r
op
"clock-frequency" property
o
f
cpu nod
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Me
n
g
riscv: Skip
c
hecking
CSR privileg
e
level in
d
ebugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
risc
v
:
sifive_u:
Upda
t
e
model and
c
o
m
p
atib
l
e str
i
ngs
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin
M
eng
r
i
scv: s
i
f
i
v
e
_u: Remo
v
e handcrafted cl
o
c
k
n
ode
s
for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin
M
eng
riscv: sifive_u
:
Fix broken G
E
M supp
o
rt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
B
i
n Meng
r
i
scv
:
s
ifive
_
u: Instantiate
O
TP memo
r
y w
i
th a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
riscv
:
sifive: Implement a mo
d
el for
S
iFive
FU
5
40
OT
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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2019-09-17
Bin Meng
ris
c
v:
rom
s
: U
p
date default bio
s
for sif
i
ve_u machine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
r
i
scv:
sifive
_
u: Change UART
n
o
d
e
name in device tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
ri
s
cv: sifi
v
e_u: Up
d
ate UAR
T
base addresses and I
R
Qs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin M
e
n
g
riscv: sifive_u: Referen
c
e PRCI clocks in
UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
riscv: sif
i
ve_u: Add PRCI
b
l
ock to
t
he S
o
C
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin Meng
riscv: sifive_u: Generate hfcl
k
and rtcclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Imple
m
e
nt P
R
CI mode
l
for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin
M
e
n
g
riscv: sifive
_
u: Update PLIC
h
art to
p
ology c
o
nfigu
r
ation
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bi
n
Men
g
riscv: s
i
f
ive_u:
Upd
a
te hart c
o
nfig
u
r
a
tion to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
B
i
n M
e
ng
riscv: sifive_u: Set
t
he minimum numbe
r
of cpus t
o
2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin
Meng
riscv: h
a
rt:
A
dd a "hartid-base" property
t
o RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in M
e
n
g
riscv: hart:
E
x
tract h
a
rt r
e
aliz
e
to a separate routin
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin
Meng
riscv: Add a si
f
ive_cpu
.
h to include both E and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_e: D
r
op sifive_m
m
io_e
m
ulate
(
)
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
B
in Meng
riscv: sifive_
e
: prc
i
: Update the
P
RCI
register block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n M
e
n
g
r
i
scv: sifiv
e
_e: prci: Fix a
typo
of hfxoscc
f
g register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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