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hw/timer/sh_timer: Silence warnings about missing fallthrough statements
2020-10-26
Bin Meng
hw/sd
/
sdc
a
r
d
:
Z
ero out fu
n
ction selection fields before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
B
i
n Meng
h
w/i
n
t
c
: Mov
e
sifive
_
p
lic
.
h to the include directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: Sort the Kco
n
f
ig opt
i
ons
i
n alphabetica
l
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Drop CONFIG_S
I
F
I
VE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
hw/ris
c
v: Alw
a
ys build riscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
hw/riscv: Mov
e
sifiv
e
_test mod
e
l
to h
w
/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifiv
e
_uart model to hw/c
h
ar
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Move
r
iscv_
h
t
i
f m
o
d
e
l
to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Move sifive_
p
lic
model
to
hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/ris
c
v: Move s
i
five_cl
i
nt
model to hw/in
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Me
n
g
hw/riscv: Move sifive
_
gpio model
t
o
h
w
/
g
pio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Move sifi
v
e_u_otp mod
e
l to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/r
i
scv: Move sifive_u_prci mode
l
to hw/mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sifive_e_p
r
ci
m
o
d
el
to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: sifive_u:
C
onnect a
D
MA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
hw/riscv
:
cli
n
t: Avoid using hard-coded timeb
a
se
frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
r
iscv: microchip_pfsoc: Hook GPI
O
con
t
rollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv:
m
icro
c
hip_pfsoc: Con
n
ect 2
C
adence GE
M
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm: x
l
nx: Set
a
ll boards
'
GE
M
'phy-addr' property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/net: cadenc
e
_gem:
A
dd a n
e
w 'phy-addr
'
prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv:
microchip
_
p
f
soc: Co
n
nect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
h
w/dma: Add SiFive
p
latfor
m
DMA c
o
ntro
l
le
r
em
u
lation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ri
s
cv: microchip_pfs
o
c: Connect
a Cadence
SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/sd:
A
dd Cadenc
e
SDHCI
emu
l
ation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w/ri
s
c
v: micro
c
hip_pfsoc:
C
onnect 5
MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/char: A
d
d Microc
h
ip P
o
larFi
r
e So
C
MMUART emulat
i
on
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
h
w/r
i
sc
v
:
Initial support fo
r
Microchip
P
olarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
ta
r
get
/
risc
v
: cpu: Set reset vector ba
s
ed
o
n the c
o
nf
i
g
u
red
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw
/
riscv: har
t
: Ad
d
a
new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
targe
t
/riscv:
c
p
u: A
d
d a ne
w
'res
e
tvec' propert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-ci/open
s
bi: U
p
d
a
te GitLab
CI to build gene
r
ic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n
Meng
hw/riscv: sp
i
ke:
C
h
ange the default bios to
use gen
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
M
e
ng
hw/riscv: Use
p
re-built bios image of generi
c
platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
roms/M
a
kefile
:
Build the gener
i
c
platform for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
rom
s
/opensbi:
U
p
grade from v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
n
g
con
f
igure: Create
s
ymbol
i
c
links for pc
-
bio
s
/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
hw
/
ri
s
cv: si
f
ive_u:
A
dd a dummy L2 cache controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
en
g
h
w
/sd
:
Correct the maximum size
o
f a Standard Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
h
w
/
s
d: F
i
x incorrect popul
a
ted functi
o
n swi
t
ch sta
t
us
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
h
w
/ri
s
cv:
sifiv
e
_
e
: Corre
c
t
debug blo
c
k
size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
hw/riscv: Modif
y
MROM size to end at 0x1
0
0
0
0
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n Meng
hw/riscv: v
i
rt:
So
r
t the SoC
memmap ta
b
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
eng
MAI
N
TAIN
E
RS: A
d
d an ent
r
y for O
p
enSBI
f
ir
m
ware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: sifive_u: Add a dummy D
D
R
m
e
m
o
ry con
t
roller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
h
w
/riscv: sifi
v
e_u: So
r
t th
e
SoC me
m
m
ap ta
b
le entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
ve_u: Suppo
r
t
d
ifferen
t
boot
s
our
c
e per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: sifive
:
C
h
ange SiFive E/
U
CPU res
e
t vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
t
a
rget/
r
iscv: Rename IBEX
CPU in
i
t
rou
t
i
ne
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_u: Add
a new property msel
f
or MSE
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv: sifi
v
e_
u
: Rename serial
prope
r
t
y get/
s
et
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/ris
c
v: sifive_u: Add reset functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: si
f
ive
_
gpio: Do not bli
n
dly tr
i
gger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
en
g
hw/riscv: sifive
_
u: Hook
a GP
I
O
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpi
o
: Add a new
'
ngpio' pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sifive_gpio: Clean up
t
he codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv
:
sifive
_
u: Generate
device
t
r
e
e node for OT
P
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive
_
u: S
i
mplif
y
th
e
GEM IRQ
c
onnect
c
ode
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw
/
ris
c
v: opentitan: Remove the riscv_ prefix o
f
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v: s
i
f
i
ve
_
e: Remove
t
h
e
r
is
c
v_ pref
i
x of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v: Kee
p
the CPU init routi
n
e names consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
ri
s
cv: Ge
n
eralize CPU init routine for t
h
e imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Ge
n
era
l
ize CPU init routine
f
or the
g
cs
u
C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
s
cv: G
e
ne
r
alize CP
U
i
nit rout
i
ne for the ba
s
e CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/riscv: virt: Re
m
ove the riscv_
p
r
e
fi
x
of the machi
n
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
hw
/
riscv
:
sifive_u: Remove
the riscv_ pr
e
fix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
ris
c
v
:
Change the
default b
e
havior
i
f no -bi
o
s option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Meng
ris
c
v:
S
u
p
p
r
e
ss
t
h
e error report fo
r
QEM
U
t
esting with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
B
in Meng
r
oms: opensb
i
: Upgrade fr
o
m v0
.
6
to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/
r
iscv
:
Generate corr
e
ct "
m
m
u
-type" for
3
2
-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
i
n Meng
riscv
/
sifive_u: Add a
seria
l
propert
y
to the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
gitlab-ci
.
yml: Add j
o
bs to
b
ui
l
d OpenSB
I
f
i
rm
w
are binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin M
e
n
g
riscv:
sifive_u: Updat
e
BIOS_FIL
E
N
A
ME
f
or 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Me
n
g
roms: opensbi: Add
32-bit firmware i
m
ag
e
for sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
in Meng
roms: op
e
nsbi: Upgrade from v0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Meng
h
w: net: cadence_gem: Fi
x
b
u
ild errors in DB_PRINT
(
)
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
r
iscv: virt
:
A
l
low PCI address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
r
i
scv: sif
i
ve_u: Add e
t
hernet0 to the alia
s
e
s
no
d
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
ri
s
c
v
: hw:
Drop "clock-freq
u
ency" property of
c
pu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-10-28
Bin Meng
riscv
:
Skip checking CSR priv
i
l
e
ge level in debu
g
ger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
if
i
v
e
_u: U
p
d
ate model
and compatible
s
t
r
ings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifi
v
e_u:
Remove
h
a
n
d
c
rafted clock n
o
des for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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|
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2019-09-17
Bin
M
en
g
risc
v
:
sifive_u: Fix broken
G
EM support
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
riscv: sifive_u: Instantiate OTP memory
with a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin M
e
ng
riscv: sifive: Implem
e
nt a mo
d
el fo
r
SiFive FU540 O
T
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: rom
s
:
Up
d
ate default bios for
s
ifive_u machin
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: si
f
ive
_
u: Ch
a
nge UA
R
T node
n
a
me in device
t
ree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: s
i
five_u:
Upd
a
te UART base add
r
es
s
es and IR
Q
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: s
i
five_u: Reference PRCI clocks
i
n UAR
T
and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
r
i
sc
v
: sifive_u:
A
dd PRCI block to
t
he S
o
C
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv:
sifive_u: Gen
e
rate hfclk and
r
tcclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Imp
l
ement PRCI
m
odel for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
r
i
s
cv: sifive_u: Update PL
I
C hart top
o
logy
configuration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
r
iscv
:
sifive_u: Upda
t
e h
a
rt
c
onfi
g
urat
i
on
t
o reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: sifi
v
e_u: Set the minimum
n
umbe
r
o
f cp
u
s
to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
s
c
v: hart: Add
a "hartid-ba
s
e"
p
roperty to RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: hart: Extract hart realiz
e
to a separa
t
e routine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: A
d
d a sifi
v
e_cpu
.
h
t
o in
c
lude bo
t
h E a
n
d U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
r
iscv: s
i
f
ive_e: Drop sifi
v
e_mmio_emu
l
at
e
()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
r
iscv: s
i
five_e: prci:
U
pdat
e
the PRCI register
block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifive_e:
pr
c
i:
Fix a typ
o
of hfxosccfg register
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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