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hw/misc/led: Add yellow LED
2020-09-09
B
i
n
M
eng
hw/riscv: mi
c
roch
i
p_pfsoc: Co
n
nec
t
a C
a
dence SD
H
CI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/sd: Add C
a
denc
e
SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
m
icro
c
hip_pfsoc
:
Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/char: Ad
d
Microchip PolarFire
S
o
C M
M
UA
R
T emulatio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/ri
s
cv: Initial support for
Micro
c
hip P
o
larFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
e
n
g
target/riscv: cp
u
: Set reset vect
o
r base
d
on the conf
i
gure
d
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v: hart: Add a new
'
resetvec' prope
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
tar
g
et/ri
s
cv: cpu: Add
a
n
ew
'
r
e
setvec' p
r
opert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gi
t
lab-ci/opens
b
i: Upda
t
e
GitL
a
b CI to
b
uild generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw
/
riscv:
s
pike:
Change the defa
u
lt bios to use g
e
n
e
r
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/ris
c
v
: U
s
e pre-
b
uilt bios image of generic platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
roms/Make
f
ile: Build the
g
eneric plat
f
orm for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi
:
Upgrade fro
m
v
0
.
7 t
o
v
0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
configu
r
e: Create symb
o
li
c
links
f
or pc-
b
ios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: si
f
ive_u: Ad
d
a
d
ummy
L
2 cache controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
C
orrect
t
he maximum
s
i
z
e
of a St
a
ndar
d
Capac
i
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n M
e
ng
h
w
/sd: Fix incorrect populated function switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/riscv: sifi
v
e_e: Correct debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/risc
v
: Modify M
R
OM size to
end at 0x100
0
0
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
hw/riscv:
v
irt: Sort the
S
oC memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n Meng
MAIN
T
AI
N
ERS:
Add an entry for OpenSBI fi
r
mware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
s
c
v:
sifive_u: Ad
d
a dummy DD
R
mem
o
ry controll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
h
w
/riscv: sifive_u: Sort the SoC
m
emmap tab
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
hw/riscv: sifive
_
u: Support di
f
fe
r
ent boo
t
source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv: sifive: Change Si
F
ive
E/U CP
U
res
e
t
vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
targ
e
t/riscv: Re
n
a
m
e IBEX CPU init
r
outi
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifive_
u
: Add a new pr
o
perty ms
e
l
f
or MS
E
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sifive_u: Rename seri
a
l pr
o
p
erty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
h
w
/r
i
scv: sifive_u: Add reset functi
o
n
ality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
r
i
scv:
s
i
f
i
v
e_g
p
io: Do
n
ot blindly
t
rigge
r
outpu
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/r
i
scv: sifiv
e
_
u
: Hook
a
GPIO c
o
n
troller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv
:
sifive_gpi
o
: Add a ne
w
'n
g
pio' p
r
oper
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
en
g
hw/riscv: sifive_gpio: Cle
a
n
u
p the co
d
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: s
i
fi
v
e_u: Generat
e
dev
i
ce tree
n
ode for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Me
n
g
hw/riscv: s
i
f
i
ve_u: Simpl
i
fy the GEM
IRQ conn
e
ct co
d
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv: opentit
a
n
: Remo
v
e
t
he riscv_
prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/
r
iscv: sifive_e:
Remove t
h
e r
i
sc
v
_ prefi
x
of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: K
e
e
p
the CPU init
routine
na
m
es consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Generalize CPU init routine
f
or
t
he imac
u
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v: Ge
n
er
a
lize CPU init routine
f
o
r the gcsu
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv
:
G
ene
r
al
i
z
e
C
P
U in
i
t routine for the
base
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
hw/risc
v
:
v
ir
t
:
R
emove
the r
i
sc
v
_ p
r
e
f
ix of the
machin
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w
/ri
s
cv: sifi
v
e_u:
Remove t
h
e riscv_ p
r
e
f
ix o
f
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
riscv
:
Change
t
he default behav
i
or if no -bios opt
i
o
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv: Supp
r
ess th
e
error
report
f
or QEMU te
s
ti
n
g with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
roms: opensbi
:
U
p
grad
e
from v0
.
6
to v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/riscv: Gener
a
te correct "mmu-typ
e
"
for
32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
M
eng
ri
s
cv/sifiv
e
_u:
A
d
d a serial property
to the sifive
_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Men
g
gitlab-ci
.
yml: Add jo
b
s
t
o
build OpenS
B
I
firmware
binarie
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
riscv: sif
i
ve_u:
Update BI
O
S_F
I
LENAME for 32-b
i
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms: opens
b
i: Add 32-bit fir
m
ware
i
mage for
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bi
n
M
e
ng
ro
m
s: opensbi: Upgra
d
e from v0
.
5 to v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
B
in
M
eng
hw: net:
cadence_gem: Fix
b
uild errors in DB
_
PRIN
T
()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin M
e
ng
risc
v
: v
i
rt
:
Allow PC
I
address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: sifiv
e
_u: A
d
d ethernet0 to the aliases n
o
de
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
B
i
n Me
n
g
ri
s
cv: hw: Drop "clock-fr
e
quenc
y
"
p
roperty
o
f cpu n
o
d
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Me
n
g
riscv: S
k
ip checking
C
SR privile
g
e
l
evel in debug
g
er
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: si
f
ive_u: Upd
a
te model a
n
d comp
a
tible strin
g
s
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
M
eng
ris
c
v: s
i
fiv
e
_u:
R
emove handcrafted c
l
ock
nodes f
o
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Fix broken G
E
M sup
p
ort
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: si
f
ive_u: Inst
a
ntia
t
e OTP memory with a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive:
I
m
p
l
e
m
ent a model
f
or Si
F
ive FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
risc
v
: roms: U
p
date default bios
f
or
sifi
v
e_u ma
c
hine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv
:
si
f
iv
e
_u:
C
h
ange UART node name in device t
r
ee
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Me
n
g
riscv
:
sifive_u: Upd
a
te UART
b
a
se a
d
dresse
s
a
n
d IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sif
i
ve_u:
R
e
f
erence
P
RCI c
l
ocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
i
fiv
e
_
u
: Add PRCI b
l
ock
to the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
ri
s
cv: sifive_u: Generate hfc
l
k and rtccl
k
nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive: Implement PRCI model
f
or FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v: sifive_u: Update
P
LIC hart topology
c
o
n
figuration
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
en
g
r
iscv: sifiv
e
_u: Update hart
c
onfigura
t
ion to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Me
n
g
riscv: sifive_u: Set
the minimum nu
m
ber of
cpus t
o
2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Men
g
ris
c
v
:
h
a
rt
:
A
dd
a
"
hartid-base" proper
t
y to
RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: hart:
E
xt
r
a
ct h
a
rt realiz
e
to
a sep
a
rate r
o
utine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
n
g
r
i
scv:
A
dd a
s
ifive_
c
pu
.
h to inc
l
u
d
e bot
h
E
and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
r
iscv: sifive_e: Dro
p
s
i
fiv
e
_mmio_e
m
ulate()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
B
in Meng
riscv: sifive_e: prci: Upda
t
e the
P
RCI regi
s
t
e
r block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
B
i
n Meng
riscv: sifive_e: prci: Fix a typo
o
f hfxosccfg regi
s
ter
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin
Meng
ri
s
cv: sifiv
e
: Rename sifi
v
e_prci
.
{
c
, h}
to s
i
five
_
e
_prci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bi
n
Meng
riscv
:
sifive
_
u: Remove the unnecessary include of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Me
n
g
ris
c
v: roms: Remov
e
executable
a
ttribute of
o
pensbi
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Me
n
g
riscv: hw: Remove t
h
e un
n
ecessary include
of
targe
t
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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2019-09-17
Bin Meng
ri
s
cv: hw: Change
to
use qemu_log_mas
k
(LOG_GUEST_ERROR
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
B
in Meng
riscv:
hw:
C
hange
c
reate_fdt() to ret
u
rn
v
oid
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
riscv: hw
:
Remove not
n
e
ede
d
P
LIC properties
in device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Meng
riscv: hw: Use
q
emu_fdt_se
t
prop_cell() for p
r
operty
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
B
i
n Me
n
g
r
is
c
v: hw
:
Remove superfluous "linux, phand
l
e" property
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin
Meng
riscv: hw:
Rem
o
ve dupl
i
cated "hw/hw
.
h" incl
u
s
i
on
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin M
e
ng
riscv:
s
ifive_test: Add
r
e
s
et functional
i
ty
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
risc
v
: hmp: Add a command to s
h
o
w
virtua
l
memory ma
p
pings
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin M
e
ng
riscv
:
R
e
solve full path of the g
i
ven bios image
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
riscv: A
d
d a h
e
l
per routine for
finding firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
risc
v
: rv32: R
o
ot
p
age table
a
ddress
c
a
n be larger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-08-13
B
in
M
eng
risc
v
:
roms
:
Fix make rules for bui
l
ding sif
i
ve_
u
b
i
os
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-06-27
Bin Meng
riscv:
sifive_u: Upd
a
te the plic hart config to
s
u
ppor
t
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-06-27
Bin Meng
riscv: sifive_u
:
Do not
c
r
eate hard-c
o
d
e
d
phandles
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-06-24
Bi
n
Meng
riscv:
virt: Correct pci "bus-range" en
c
oding
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-03-19
Bin
M
eng
riscv: si
f
ive_u: Correct UART0's IR
Q
i
n the device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-03-19
Bin Meng
riscv: si
f
iv
e
_uart: Generate TX interrupt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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