| commit | 4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Sun, 17 Mar 2019 08:03:10 +0000 (17 01:03 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 19 Mar 2019 12:18:28 +0000 (19 05:18 -0700) | ||
| tree | c90e5a7136ad8049b0de03d2ade72a1f8969ce7e | treesnapshot (tar.gz zip) |
| parent | 6b745d4fada5c73db44f596a62e29a5dbe3fc53f | commitdiff |
riscv: sifive_uart: Generate TX interrupt
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_uart.c | diffblobblamehistory |