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target/mips: Do not abort on invalid instruction
2020-11-03
Bin
Meng
hw/ri
s
c
v
: microc
h
ip_
p
fso
c
: Map the rese
r
ved memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/riscv: m
i
crochip_pfsoc: Connect the
S
YSREG
mo
d
ule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
e
n
g
hw/misc: Add
Microch
i
p PolarFire SoC S
Y
SREG module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: mi
c
rochip_p
f
so
c
:
Conn
e
ct the IOSCB modul
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
h
w/misc: Add Microchip PolarFir
e
SoC IOSC
B
module
su
p
p
ort
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in
M
e
ng
h
w
/riscv: microchi
p
_pfsoc
:
Connect DDR memory c
o
ntroller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w/mi
s
c: Add
Microchip PolarFire
SoC DDR Mem
o
ry
C
ontrolle
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
Meng
hw/ri
s
cv: microc
h
ip_pfsoc: D
o
cument where to look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin
M
eng
hw/sd
/
s
dcard: Zero
o
u
t function
selectio
n
fields
b
e
fore
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
B
in Men
g
hw/intc
:
Move
sifi
v
e_plic
.
h
to the inclu
d
e directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: Sort the
Kconf
i
g options in alphabetic
a
l
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Dro
p
CONFIG_
S
IFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv: Alwa
y
s
b
u
il
d
riscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/r
i
scv:
Move sifive_test
m
odel to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/
r
is
c
v: Move s
i
five_uart model to hw/ch
a
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
M
ove riscv_htif model
to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mo
v
e
s
ifive_pl
i
c model to
h
w/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/r
i
scv:
Move sifive_clint mo
d
el to hw/in
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mov
e
sifive_gpio model to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mov
e
sifiv
e
_u_otp model to
h
w/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/risc
v
: Move
s
ifive_u_p
r
ci
m
odel to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
ri
s
cv: Mo
v
e sifi
v
e_e_prci model
t
o
h
w/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Me
n
g
hw/r
i
scv: si
f
ive_u: Conne
c
t
a DMA cont
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: cli
n
t: Avoid using hard-coded timebas
e
frequ
e
ncy
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
ris
c
v:
micro
c
h
i
p
_
p
f
s
oc:
H
o
ok GPIO
c
ontrollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/r
i
scv: mic
r
ochip_pf
s
o
c
:
Connect 2
Cadence G
E
Ms
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
a
rm: xlnx
:
Set all boards'
GEM 'phy-add
r
' property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw
/
net: cadence_gem: Add
a new 'phy-addr' p
r
o
p
erty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ri
s
cv: mi
c
rochip_pfsoc: Co
n
nect a
DMA cont
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: A
d
d SiFive platfo
r
m DMA
c
ontroller emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: micr
o
chip_p
f
soc: Conn
e
ct a Cadence
S
DHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
sd: A
d
d C
a
dence SDHCI
emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw
/
riscv:
m
icrochip_pfsoc:
C
onnect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw
/
ch
a
r: Add Micro
c
hip PolarFire SoC M
M
UART e
m
ulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w
/riscv: Initial supp
o
rt f
o
r Microch
i
p Polar
F
ire S
o
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
target/
r
iscv: cpu: S
e
t
r
e
s
et vecto
r
based
on
the configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
h
w/r
i
scv: hart: Add a ne
w
'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
tar
g
et
/
riscv: c
p
u: Add a new
'resetvec'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
g
itlab-ci/opensbi:
U
pdate G
i
t
Lab
C
I
to
b
uild
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: spi
k
e:
C
hange
t
he
default b
i
os t
o
u
se
generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/ris
c
v: Use pre-buil
t
bios image of generic platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Ma
k
efile:
Bui
l
d th
e
generic platf
o
rm f
o
r
R
ISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi: Upgrade from v0
.
7 t
o
v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Men
g
conf
i
gure
:
Create symboli
c
links for pc-bios/
*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Men
g
hw
/
r
i
scv:
s
if
i
ve_u:
A
dd
a
dummy L2 cach
e
c
o
ntro
l
le
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Me
n
g
hw/sd: Correct t
h
e ma
x
imum
s
ize
of a Standard C
a
p
a
city
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
in M
e
ng
hw/sd: Fix i
n
cor
r
e
c
t populated funct
i
on
switch
status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/riscv: sifive_e:
C
or
r
ect debug block
size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Men
g
h
w/riscv: Mo
d
ify
MROM size
to
end at 0x100
0
0
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
hw/ris
c
v: virt: Sort the SoC memma
p
table e
n
tries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
e
ng
M
AINTAINERS: Add an entry for OpenSBI firm
w
ar
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Add a dummy DDR memory co
n
trol
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifiv
e
_
u:
S
ort
t
h
e
SoC memm
a
p
table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifive_u
:
Sup
p
ort di
f
f
eren
t
boot source
p
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
r
iscv: si
f
ive: Change SiFive E/U CPU reset
vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
target/riscv: Rename IBEX CPU init rout
i
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
hw/r
i
s
c
v: sif
i
ve_u: Add a new property mse
l
for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv: sifive_u:
R
ename serial
p
ropert
y
get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
c
v
: sifive_u: Add reset
func
t
ionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw
/
riscv: s
i
five_gpio: Do n
o
t blindly tr
i
g
ge
r
outp
u
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifiv
e
_u: H
o
ok a
G
PIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
h
w
/ri
s
c
v: sifive_gpio: Ad
d
a
n
ew 'ng
p
io' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
iscv:
s
ifive_g
p
io: Clean up t
h
e co
d
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifive_u:
Ge
n
erate device tre
e
no
d
e for
OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
h
w
/riscv: sifive_u:
S
im
p
lify the GEM IR
Q
connect c
o
de
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv: opentitan:
R
emo
v
e t
h
e ri
s
cv_ p
r
efix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: sif
i
ve_e
:
Remove the riscv_
p
ref
i
x of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
riscv
:
Keep the CPU init routine names consis
t
ent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gener
a
lize CPU init
r
outi
n
e
f
o
r
the imac
u
CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
riscv:
Generaliz
e
C
PU init rout
i
ne
for t
h
e g
c
su
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gen
e
ralize CPU init
r
o
u
tine for
the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/riscv:
virt:
R
e
m
ove the riscv_ prefix
o
f the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
M
eng
hw/risc
v
: sifi
v
e_u
:
Remove
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
n
g
r
i
s
cv: Change
t
he de
f
ault
b
ehavior
i
f no -bio
s
option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
ri
s
cv: Suppress the er
r
or repo
r
t
for QEMU test
i
ng with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
roms:
o
pensbi: Upgrade from v0
.
6
t
o v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Me
n
g
hw/riscv: Ge
n
erat
e
corr
e
ct "mmu
-
t
ype" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin M
e
ng
riscv/sifiv
e
_u: Add a seri
a
l property to
the sifiv
e
_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
gitlab-ci
.
y
m
l: Add jobs to build O
p
enSBI fir
m
ware binari
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bi
n
Meng
ris
c
v:
sifive_
u
:
U
pdate BIOS_FILENAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bin Meng
roms:
opensbi: Add
3
2-b
i
t firmware image f
o
r
s
ifive_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bi
n
Meng
roms
:
opensbi: Upgrade from v0
.
5
t
o
v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-03
Bin
M
eng
hw: net: cadence_gem: Fix
build
e
rrors in
DB
_
PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-02-27
Bin
Men
g
riscv:
virt
:
Allo
w
PCI address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-10-28
Bin Meng
riscv: sifi
v
e_u
:
Add et
h
ernet0 to the a
l
iases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-10-28
Bin
Meng
r
iscv: hw: Drop "cloc
k
-frequency
"
prope
r
ty of
cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-10-28
B
i
n
Meng
ris
c
v
:
Skip checkin
g
CSR privi
l
ege level in
d
e
bugge
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
r
iscv: sifive_u: U
p
d
ate mo
d
el
and c
o
m
p
atible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
r
iscv:
s
ifive_u:
Rem
o
v
e
ha
n
dcrafted clock nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
B
i
n
Meng
riscv: sifive_u: Fix broken GEM
support
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
B
in Meng
riscv: sif
i
ve_
u
: In
s
tanti
a
te OTP memor
y
wit
h
a se
r
ia
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
riscv:
s
if
i
ve: Implement
a
model for SiFive
F
U540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Me
n
g
ri
s
cv: roms:
Update
d
e
f
aul
t
bios
f
or
s
ifive
_
u mac
h
ine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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2019-09-17
B
in Meng
riscv: sifi
v
e_u: Cha
n
ge UA
R
T nod
e
n
ame in device
t
ree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin
M
en
g
ri
s
cv: sifive_u:
U
pdate UART base a
d
dresse
s
an
d
IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin Meng
r
i
scv: s
i
five_u:
R
eference PRCI clocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
Bin M
e
n
g
riscv: si
f
ive_u: Add
P
RCI blo
c
k
t
o
the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Meng
risc
v
:
sifive_u: Generate hfclk and rtcclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
B
in M
e
ng
r
iscv: sif
i
v
e
: Implement P
R
C
I model for FU540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin M
e
ng
riscv: sifive_
u
: U
p
d
ate PLIC hart
t
o
po
l
ogy configu
r
a
tion
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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