hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
commit3400b15bbe0fbc672fee9a18268154b07a1fed2e
authorBin Meng <bin.meng@windriver.com>
Wed, 28 Oct 2020 05:30:02 +0000 (28 13:30 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 3 Nov 2020 15:17:23 +0000 (3 07:17 -0800)
tree8481d450f42487041164e70c0181c33983c0a1e7
parent08b86e3b8f5209b1c39f22a6d367f347eaf0f8be
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support

The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.

This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
MAINTAINERS
hw/misc/Kconfig
hw/misc/mchp_pfsoc_dmc.c [new file with mode: 0644]
hw/misc/meson.build
include/hw/misc/mchp_pfsoc_dmc.h [new file with mode: 0644]