| commit | 05d9d0359e6da7dc8255712d745d079a04fa5ae5 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sat, 22 May 2021 18:16:15 +0000 (22 20:16 +0200) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Thu, 24 Jun 2021 14:48:07 +0000 (24 16:48 +0200) | ||
| tree | b2d8e297ad3466988d87e5b30fa161ae0039d0b4 | treesnapshot (tar.gz zip) |
| parent | a071578b93e850dcbebbe2c0cfe86e7977ddffa7 | commitdiff |
target/mips: Do not abort on invalid instruction
On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
| target/mips/tcg/translate.c | diffblobblamehistory |