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target/mips: Rewrite complex ifdef'ry
2020-09-09
Bin Men
g
hw/riscv:
m
ic
r
o
c
hip_p
f
s
o
c: Co
n
nect a Cadence S
D
H
C
I
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/sd: Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: microch
i
p_pfsoc:
C
onne
c
t 5 MM
U
ARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Men
g
hw/char
:
A
d
d Micr
o
ch
i
p PolarFi
r
e SoC MMUART emulat
i
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Initial
suppo
r
t
for Mic
r
oc
h
ip PolarFi
r
e SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: cpu: Set rese
t
v
e
c
tor based on
the conf
i
gured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: hart: Add a n
e
w 'resetvec'
pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: cpu:
A
d
d a new 're
s
etv
e
c
' pr
o
p
e
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitl
a
b-ci/op
e
nsbi:
U
pdate GitLab CI
to b
u
ild generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
hw
/
risc
v
:
spike:
Ch
a
nge the defa
u
lt bios to use
generi
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/ris
c
v: Use pre-built bios imag
e
of generic
pla
t
form
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Makefile: Build the
generic p
l
atform for
RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
r
o
ms/opensbi: Upgrade
from v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
confi
g
ure: Create symbol
i
c lin
k
s fo
r
pc-bio
s
/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
hw/riscv: sifive_u
:
Add a dummy
L
2 cache controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n Meng
hw/sd: Correct th
e
maximum size of
a Standard Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Fix inco
r
rect populated
f
u
nc
t
ion switch
status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Men
g
h
w
/
r
is
c
v: sifive_e: Correc
t
debu
g
blo
c
k size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Men
g
hw/ris
c
v
: Modify
MROM size
to end
at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/r
i
scv:
virt: S
o
rt the SoC m
e
m
m
a
p
ta
b
le entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINTAINE
R
S: Ad
d
an ent
r
y
f
or Open
S
BI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
iscv: sifive_u
:
A
d
d a dummy
D
D
R memor
y
co
n
troller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
e
ng
hw/risc
v
:
sifive
_
u: Sort the
S
o
C
memmap
table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
i
s
cv: sifi
v
e_u: S
u
pport different boot source pe
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
ris
c
v: s
i
five: Ch
a
ng
e
SiFive E/U
CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
target/ris
c
v: R
e
name
IBEX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw
/
r
iscv:
sifive_u: Add a new proper
t
y msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive
_
u: Rename
se
r
ial pr
o
perty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/
ris
c
v:
s
ifive_u:
Add
r
e
set fu
n
ctionali
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/r
i
s
cv:
s
if
i
ve_gpio: D
o
n
o
t bl
i
ndly tri
g
ger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifi
v
e_u
:
Hook a
G
PIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio:
Add a new 'ngpio' pro
p
erty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Clean up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
hw/r
i
scv: sifive_u: Generate
device tree
n
ode for
OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
si
f
i
v
e_u: Simplify th
e
G
E
M IR
Q
connect co
d
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
hw/riscv: opent
i
tan: Rem
o
ve
the risc
v
_
p
r
e
fix
of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
v
e
_e:
R
emov
e
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
riscv: K
e
ep
the CPU i
n
it
rou
t
i
ne name
s
consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
scv: Generalize CPU init routine
for the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Generalize CPU i
n
it routine fo
r
the gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
riscv: Generalize CP
U
i
n
i
t routin
e
for the base
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w
/ris
c
v
: virt: Remove the ris
c
v
_
pr
e
f
i
x of the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Men
g
hw/riscv: sifive_u: Remo
v
e the r
i
sc
v
_
p
re
f
ix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
r
i
scv: Cha
n
ge the default behavior if no
-
bios
o
ption
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Meng
ri
s
cv:
S
upp
r
ess the
erro
r
report for QEMU testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
r
o
ms: o
p
ensbi: Upgr
a
de from v0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bi
n
Meng
hw/riscv:
G
enerat
e
correct "mmu-type" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
i
n Meng
r
iscv/sif
i
v
e_u: Add a serial
p
ropert
y
to the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
g
itlab-
c
i
.
yml: Ad
d
jobs to build OpenSBI firmware b
i
naries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n Meng
ris
c
v: s
i
fi
v
e_u: Update BIOS_FILENAME fo
r
32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
r
o
ms: opensbi: Add
3
2-bit f
i
rmware
i
ma
g
e fo
r
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n Me
n
g
r
o
ms: opensbi: Upgrade from v0
.
5 to
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Meng
hw: net:
c
a
d
ence_g
e
m: Fix
b
u
ild er
r
ors in DB_PR
I
NT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv:
virt: Al
l
ow PCI address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
B
in Meng
riscv: sifive
_
u:
A
dd ethernet0 to
t
he aliases nod
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin
M
eng
riscv: hw: Drop "clock-
f
requency
"
prope
r
ty of c
p
u
n
odes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: Skip checking CSR privilege level in deb
u
gge
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
ris
c
v: si
f
ive_u: Update mode
l
an
d
compa
t
ible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
e
ng
riscv
:
s
ifive_u
:
Remove handcrafted
cl
o
ck nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
e
n
g
riscv: sifive_u: F
i
x brok
e
n GEM suppo
r
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Me
n
g
riscv: sifive_u: Instantiate OTP mem
o
ry with a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
risc
v
:
sifive: Implemen
t
a model
f
or SiFive FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: roms:
Update
d
ef
a
u
l
t bios for sifive_u m
a
c
h
ine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u:
Chang
e
UART node name
i
n de
v
ice tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
si
f
ive_u: U
p
date U
A
RT base ad
d
r
e
sses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifi
v
e_u: Referenc
e
PR
C
I clocks in UART an
d
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Add PR
C
I block to the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: s
i
five_u: Generate
h
f
c
lk and rtcclk
n
o
d
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
sc
v
: sifive: I
m
plement
P
R
C
I
model for
F
U
540
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifive_u:
U
pdate PLIC hart
topolog
y
confi
g
u
r
at
i
o
n
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: si
f
ive_u: Updat
e
hart
c
onfigur
a
t
i
on to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
ris
c
v: sifive_
u
: Set the minimum number of cpus to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: h
a
rt: Add a
"hartid-bas
e
" pr
o
per
t
y to RISC-V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
M
e
ng
riscv: hart
:
Extract hart rea
l
ize to a
separate
r
outine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
ng
riscv: Add
a s
i
five_cpu
.
h to include both E and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: sifive
_
e
: Drop sifive_mmio_e
m
u
late()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: s
i
five_e: prci: Up
d
ate th
e
PR
C
I register b
l
o
c
k
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_
e
: prci: Fix
a
typo of hfxosccfg
reg
i
ster
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Rename
sifive_prci
.
{c, h} to
s
i
f
ive_e_prci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
riscv: sifive_u: Remove the unnecessary incl
u
de of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Me
n
g
r
i
s
c
v: ro
m
s: Remove exec
u
table attribu
t
e
of opensbi
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
riscv: hw
:
Re
m
ove
t
he unn
e
cessar
y
i
nclude
o
f
t
arget
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin
M
e
n
g
r
iscv: hw: Change
t
o use qemu_log_mask(LOG_G
U
EST_ERROR
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin
M
eng
r
iscv: hw: Change cre
a
t
e_fdt
(
) t
o
retur
n
void
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin Meng
riscv: hw: Remove
n
ot neede
d
PLI
C
properties in device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin M
e
ng
riscv
:
hw:
Use qemu_f
d
t_setpro
p
_cell() for pro
p
erty
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
r
i
scv:
hw:
R
emove
superfluous
"linux, ph
a
ndle" p
r
o
pert
y
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin Meng
riscv:
h
w: Remove d
u
p
lica
t
ed "hw/h
w
.
h" inclus
i
on
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: si
f
ive_t
e
st:
A
dd
reset functionality
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
h
mp: Add a
comma
n
d to show v
i
rt
u
al memory mappin
g
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: Resolv
e
full path of th
e
g
i
ven b
i
os image
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin M
e
ng
ris
c
v: Add a
helpe
r
routi
n
e
for findi
n
g firm
w
are
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin Meng
riscv
:
rv32: Roo
t
page table a
d
d
ress can be la
r
g
e
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-08-13
Bin Meng
riscv: roms: Fix make rules f
o
r building sif
i
v
e
_u bios
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-06-27
Bi
n
Meng
riscv: sif
i
ve_u: Update t
h
e
plic hart co
n
fig to support
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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|
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2019-06-27
B
i
n Meng
riscv: sifive_u: Do not create hard-coded phand
l
es
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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|
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2019-06-24
B
i
n M
e
ng
r
i
sc
v
: virt: Correc
t
pci
"
b
u
s-range" encodin
g
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-03-19
B
i
n Meng
riscv: sifive_u: Co
r
re
c
t UART0'
s
IRQ
i
n the device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-03-19
Bin Meng
riscv: sifive_uart: Generate TX int
e
rrupt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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