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hw/mips: Add Loongson-3 machine support
2020-12-10
Bin Meng
t
a
r
g
e
t
/i386: seg
_
helper: Correct segm
e
nt
selector nul
l
ificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
B
in Meng
hw/sd: Fix
2
GiB card C
S
D regi
s
ter values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Me
n
g
h
w
/
riscv: mi
c
r
o
c
hip_pfsoc: Hook th
e
I2C1 controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n M
e
ng
hw/riscv: microchip_p
f
s
oc: Correct
D
D
R mem
o
ry
map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/ris
c
v: microchip_pfsoc: Map the reserved
memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w/risc
v
: microchip_pfsoc: Connec
t
t
h
e SYSREG m
o
dule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/mis
c
: Add
M
i
c
rochip PolarFire SoC
S
Y
S
REG modu
l
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/riscv: mic
r
ochip_pf
s
o
c
: Connect the IOSCB
m
odule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/misc: Add Micr
o
chip
P
o
l
arFire SoC IOSCB module support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
M
en
g
hw/riscv: mi
c
rochi
p
_
p
fso
c
: Co
n
nect D
D
R
memory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/mi
s
c: Add Microchip PolarFir
e
SoC DDR Memory C
o
ntroller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw
/
riscv: microchip_pfsoc: Docume
n
t
w
here to look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd
/
sdcard: Z
e
r
o
o
ut fun
c
tion
s
electio
n
f
ields bef
o
r
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
B
in
Meng
hw/i
n
tc: Move
sifive_plic
.
h to the include directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Sort t
h
e Kconfig op
t
ions in alp
h
a
betical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Drop CON
F
IG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv:
A
lways bui
l
d ris
c
v_har
t
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Mov
e
sifive
_
test
mo
d
el
t
o
h
w
/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifive_uart model to hw/ch
a
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
isc
v
: Mo
v
e riscv_hti
f
mod
e
l to
h
w/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: Move sifi
v
e_
p
lic
m
ode
l
to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/risc
v
:
Move sifive_
c
li
n
t mode
l
to hw/
i
ntc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/
r
iscv: Mov
e
s
i
fi
v
e
_
gpio mo
d
el to hw/
g
p
i
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/risc
v
: Mov
e
s
i
five_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: M
o
ve
si
f
i
ve_u_prci model
t
o hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Move sifive_e_
p
rci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ri
s
cv:
sifive_
u
: Co
n
nect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: cli
n
t: Avoid using har
d
-coded ti
m
ebase frequ
e
ncy
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw
/
ris
c
v: microchip
_
pfsoc: Hook
GP
I
O controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw
/
r
iscv: microchip_pfsoc: Connect 2
C
adence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm: xl
n
x: Set
a
ll boards' GEM 'phy
-
addr' property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/
n
et: cadence_gem: Add
a new
'
phy-add
r
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/risc
v
: microch
i
p_pfsoc:
C
onnect a DMA
c
ontrolle
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: Add S
i
Five platform DMA controller emula
t
ion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ri
s
cv
:
microc
h
ip_pfs
o
c: Con
n
e
ct a
C
aden
c
e SD
H
CI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/sd: Add Cadence SDHCI em
u
latio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/ris
c
v
: mi
c
rochip_pfs
o
c:
Co
n
nect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/char
:
Add Microchip PolarFire SoC
M
MUART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
h
w
/
r
i
scv: In
i
tial support for M
i
crochip
P
olarFire
S
oC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
target/
r
i
scv:
c
pu: Set reset vector ba
s
e
d
on
the
configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: hart:
A
dd a new 'r
e
s
e
tv
e
c' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target
/
riscv: cp
u
: Add a
new
'
resetvec' propert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-
c
i/o
p
en
s
bi: Update
G
itLab CI to
b
uild gen
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: s
p
ike: Change t
h
e
def
a
ult
b
ios
t
o
use
ge
n
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
hw
/
r
i
s
c
v: Use pr
e
-built bios image of generic pl
a
tform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
n
g
roms/Ma
k
efile: Build the generic platform f
o
r RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
r
o
ms/opensbi: Upgr
a
d
e
f
rom
v
0
.
7
t
o v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
con
f
i
gure
:
Create symbol
i
c
l
inks for
p
c-bi
o
s/*
.
e
lf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
en
g
hw/riscv: sifive_u: Add
a
dummy L2
c
ache control
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Correct th
e
ma
x
imum
siz
e
o
f
a
S
tandard Capac
i
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Fi
x
incorrect p
o
p
u
lated functi
o
n switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
B
in Meng
hw/riscv: sifive_e: Correct debug block s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
h
w/riscv: Modif
y
M
ROM size to end
at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
h
w
/riscv: virt: Sort the SoC m
e
mma
p
tab
l
e entr
i
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINTA
I
NERS: Add an entry for
O
pe
n
SBI firm
w
are
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv:
s
i
five_u: Add
a dummy DDR
m
emory
contr
o
l
ler
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_u:
S
ort the SoC memmap table
e
ntries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/ri
s
cv: sif
i
ve_u:
S
upport different boot
s
ource per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: sifiv
e
: Change SiFive E/U CPU rese
t
v
e
ctor
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
target/riscv:
Rename IBEX CPU ini
t
r
ou
t
in
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
sifive_u: Add a new property
m
sel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
c
v: s
i
five_u: Rename se
r
ial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: sifive
_
u: Ad
d
reset fu
n
ctionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
five_gpio: Do not blindly trigger
outp
u
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw
/
ri
s
cv: sifiv
e
_u
:
Hook a GPI
O
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
h
w/riscv: s
i
five
_
gpio: Add a
new 'ngpio' prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
h
w/riscv: sifive
_
gpio: Clean
u
p
the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_u
:
Generate devi
c
e
tree node
f
or OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv
:
sifiv
e
_
u
:
Simpl
i
f
y
the
G
EM IRQ
c
o
nn
e
c
t code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv
:
o
pentitan:
Remove the riscv_ p
r
efix of
t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w
/ri
s
cv: sifiv
e
_e:
Remove the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
riscv: Keep t
h
e CPU init routi
n
e n
a
mes consist
e
n
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Ge
n
eralize CPU
init rout
i
ne for the
i
ma
c
u CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
riscv:
G
ener
a
lize
C
PU init routine
f
o
r t
h
e g
c
su
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
riscv: Generalize CP
U
i
nit routi
n
e for the b
a
s
e CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w/
r
iscv: virt
:
Remove the
ri
s
cv_ prefix of th
e
ma
c
hine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw
/
r
iscv: sif
i
ve_u
:
R
emove the ri
s
cv_ prefix of
t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
r
i
scv: C
h
a
n
g
e the default
b
e
havior if
n
o -bios o
p
tion
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-03
Bin Meng
riscv: Su
p
p
re
s
s the error repor
t
f
o
r QEMU testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
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commitdiff
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tree
2020-04-29
Bin Me
n
g
ro
m
s: opensbi: Upgrade from v0
.
6 to
v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-04-29
B
in Meng
hw/riscv: Gene
r
at
e
correct "mmu-type" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-04-29
B
i
n
M
eng
r
i
scv/sifive
_
u: A
d
d a serial pro
p
erty to the si
f
i
v
e_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
Bin
M
eng
gitlab-ci
.
yml: Add jobs to build OpenS
B
I
firmware b
i
naries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
B
i
n Meng
riscv:
si
f
ive_
u
: U
p
date B
I
OS_FILENAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-17
Bin Meng
roms: o
p
ensbi: Ad
d
32-bit firmwa
r
e ima
g
e fo
r
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms
:
opens
b
i: Upgrad
e
from v0
.
5
t
o
v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin M
e
ng
hw: net: caden
c
e_g
e
m: Fix
b
ui
l
d errors in
D
B_PR
I
NT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
ris
c
v: virt:
A
llow
P
CI
ad
d
ress 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv:
sifive_u
:
Add ethernet0
to
t
he al
i
a
s
e
s
n
od
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bi
n
Meng
riscv
:
hw: D
r
op "clock-fre
q
uenc
y
" property of cpu no
d
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin
M
eng
riscv: Skip che
c
king CSR privilege level in debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: s
i
five_
u
: Upda
t
e
model an
d
compatible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
s
cv: si
f
ive_u: Remove ha
n
dcrafted clock nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive_u: F
i
x
b
roken GEM support
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
:
sifi
v
e_u: Instan
t
ia
t
e OT
P
mem
o
ry with a seria
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
ris
c
v: sifive: Implement a model for SiFiv
e
FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv:
r
o
m
s: Update d
e
f
a
ult bios for sifive
_
u
m
a
c
hine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
r
iscv: sifive_u
:
Change UART nod
e
name in device tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifi
v
e_u: Updat
e
UART base a
d
d
r
esses
a
nd
IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: si
f
iv
e
_u
:
Reference
P
RC
I
clocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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