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hw/mips: Add Loongson-3 machine support
2020-12-10
Bin Meng
ta
r
g
e
t/i
3
86: seg_helper:
C
o
rrect segmen
t
sele
c
tor nullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bi
n
M
eng
hw/sd: Fix 2 GiB card CSD register values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/ri
s
c
v
: microchip_pfsoc: Hook the I2C1 contro
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/risc
v
: microch
i
p
_pfsoc: Co
r
r
ect D
D
R mem
o
r
y
map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/
ri
s
cv: mic
r
och
i
p_
p
fsoc
:
Map the
res
e
rved
memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Men
g
hw/ris
c
v:
m
icroc
h
ip_pfsoc: Connect the SYSR
E
G
modul
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/
m
isc: Add Microchip PolarFire
SoC SY
S
R
E
G module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/r
i
scv: m
i
crochip_pfsoc:
C
onnect the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Add
Micr
o
chip PolarFire SoC IOSCB mo
d
ule support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
hw/ri
s
cv: microchip_pfsoc: C
o
nn
e
ct DD
R
memory cont
r
oll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/misc: A
d
d
Mic
r
och
i
p PolarF
i
re SoC DDR
M
emory
Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/riscv: microchip_pfsoc: Document w
h
ere to look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd/sd
c
ar
d
: Zero out
f
uncti
o
n s
e
lection
f
i
el
d
s before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bi
n
Men
g
hw/intc: Move sifive_plic
.
h to the
i
nc
l
ud
e
directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v
: Sort
t
he Kconfig
options in alpha
b
etical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w
/riscv: Drop C
O
NFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/r
i
scv: Always build riscv_har
t
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Move si
f
ive_test model to hw/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
M
ov
e
s
if
i
ve_ua
r
t
model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Move riscv
_
hti
f
mode
l
to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: Mo
v
e
s
i
five_plic m
o
del
t
o
hw/in
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Me
n
g
hw
/
r
i
scv:
M
ove sif
i
ve_
c
lint
model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv
:
Move sifive_gpio model
t
o hw
/
gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifiv
e
_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv: Move
si
f
iv
e
_u_prc
i
model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: Move sifive_
e
_prci
m
o
d
e
l to
hw/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
eng
hw/riscv: sif
i
ve_u: Co
n
nect a D
M
A controll
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv:
c
lint: Avoid using ha
r
d-coded t
i
mebase fr
e
quency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/ris
c
v: microchip_pfsoc: Hook GPIO
c
ontrollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
microchip_pfsoc: Connect 2 Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm: xlnx: Set all
b
o
ards' GEM 'ph
y
-addr' property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/n
e
t: cadence_ge
m
: Add
a n
e
w 'p
h
y-addr
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv:
microchip_pfsoc: Co
n
nect
a
DMA control
l
er
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: Add SiFive
plat
f
orm DMA
controller e
m
ul
a
tion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: microchip_pfsoc: Connect a Cadence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw
/
sd: Add Cadence SD
H
CI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: microchip_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Men
g
hw/char: Add Microchip PolarFi
r
e SoC MMUART emulati
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: I
n
itial
s
upp
o
rt f
o
r Microch
i
p PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
target/riscv: cpu: S
e
t reset vecto
r
base
d
o
n
the confi
g
u
red
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: hart: Add a new 'r
e
setvec
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
targ
e
t
/
r
iscv:
c
pu:
A
dd a new 'rese
t
ve
c
' prope
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
gitlab-c
i
/opensbi: Update GitLab CI to bu
i
ld generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv:
s
p
i
ke
:
Ch
a
nge the de
f
a
u
lt
bios
t
o use ge
n
er
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw
/
risc
v
: Use pre-built bios im
a
ge of generic
p
l
a
tfor
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Makefile:
B
uild the ge
n
eri
c
platform fo
r
RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
roms/opensbi: Upg
r
ade from
v0
.
7 t
o
v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
co
n
figure: Create symb
o
lic links for pc-bio
s
/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifive
_
u: Add a dummy L2
cach
e
controll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
h
w
/sd: Correct the maxi
m
um size of
a S
t
a
n
dard Cap
a
city
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw
/
sd: Fix incor
r
ec
t
populate
d
fun
c
tio
n
swi
t
ch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bi
n
Meng
hw/ri
s
cv: sifi
v
e_e
:
Correct
d
ebug block s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
h
w
/risc
v
: Modify MROM si
z
e to end at
0
x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
e
ng
hw
/
riscv: vi
r
t:
S
ort the SoC memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
MAINTAINERS: Add an ent
r
y fo
r
O
penSBI
firm
w
are
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: s
i
five
_
u: A
d
d a dummy DDR memory cont
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Sort t
h
e SoC m
e
mmap table en
t
ries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
r
i
s
c
v: sifive_u: S
u
pp
o
r
t
di
f
ferent bo
o
t source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
e
n
g
hw/ris
c
v
:
sifive: Ch
a
nge SiFive E/
U
CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
target/riscv: Re
n
ame IBEX CPU i
n
it r
o
utin
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv:
s
ifiv
e
_u: A
d
d a
n
ew property msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Re
n
ame serial pro
p
erty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv
:
sifive
_
u: Add
r
e
set function
a
lity
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio: Do n
o
t blindly trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_u: Ho
o
k
a
GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: s
i
five_gpio:
Add a new 'ngpio'
p
roperty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Me
n
g
hw/ri
s
cv: si
f
i
v
e_gpio
:
C
l
e
a
n up t
h
e codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Men
g
h
w/ris
c
v: sifive_u: Gener
a
te device tree
no
d
e fo
r
O
TP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
hw/riscv: si
f
ive_u: Simplif
y
the GEM IRQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: open
t
i
t
a
n: Re
m
o
v
e the ris
c
v_ prefix of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_e:
Remove the
r
i
s
cv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Ke
e
p
the C
P
U init routine names consis
t
e
nt
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
ris
c
v
:
Generaliz
e
CPU init routin
e
for
the imac
u
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ri
s
cv
:
Gen
e
ralize CPU init
rout
i
ne
fo
r
the gcsu
CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
riscv: Generalize
C
PU init
r
o
utine for the b
a
se CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw
/
riscv: virt: Remove
t
he riscv_ prefix of
t
he machin
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
hw/riscv
:
sif
i
v
e
_u: Re
m
ove the riscv_ prefix of
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv:
Change the defaul
t
behavior if no -bios optio
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
M
eng
riscv: Su
p
pr
e
ss the error
re
p
ort f
o
r QEMU testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
B
in Meng
r
o
m
s
: opensbi: Up
g
r
a
d
e fr
o
m v0
.
6 to
v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-04-29
Bin M
e
ng
hw/riscv: Generate
correct "
m
m
u
-type" for
3
2-bit
machi
n
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-04-29
Bin Meng
riscv/sifive_u: A
d
d a serial p
r
operty to the sifive_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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tree
2020-03-17
Bin
M
e
ng
gitlab
-
ci
.
yml: Add jobs to
bui
l
d Op
e
nSBI
fi
r
m
w
are binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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tree
2020-03-17
Bin Meng
riscv: s
i
fi
v
e_u:
Update BI
O
S
_
FILENAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
B
in Meng
roms: opensbi: Add 32-bit firmware image
f
or sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-17
Bin Meng
roms: opensbi: Up
g
rade from v0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-03
Bin Me
n
g
hw
:
net: cad
e
nce_gem: Fix bu
i
ld erro
r
s in DB_
P
RINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-02-27
Bin Meng
riscv: vi
r
t: A
l
low PCI add
r
ess 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin Meng
r
i
scv: sifive_u: A
d
d ethe
r
net0 to the alias
e
s
no
d
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin M
e
ng
riscv: hw: Dr
o
p
"clock-frequency" property o
f
cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Men
g
riscv: Skip
ch
e
cking CSR privi
l
e
g
e
l
ev
e
l
in deb
u
g
ger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sif
i
ve_u: Update model and compatib
l
e strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: sifive
_
u: Remo
v
e handcrafted cl
o
c
k
n
o
des for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
s
i
five
_
u: Fix b
r
o
ken GEM support
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: sifive_
u
:
Instan
t
iate OTP memory
w
i
t
h
a
seria
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
sif
i
ve: I
m
plement a
m
o
del for SiFive FU540
OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
:
r
oms: Update d
e
fault
b
ios for sifive_u machin
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin
M
e
n
g
riscv:
s
i
fi
v
e_u: Change
UAR
T
node n
a
me in
device tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: sifive_u:
Update U
A
RT base
a
ddresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
ris
c
v
:
s
i
fi
v
e
_
u
: Reference
PRCI clocks in UART a
n
d
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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