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hw/rx/rx-gdbsim: Fix memory leak (CID 1432307)
2020-11-03
Bin Meng
hw
/
riscv: microchip_p
f
soc: Hoo
k
the I2C1 co
n
trolle
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv:
m
icrochip_pfsoc: Cor
r
e
c
t D
D
R m
e
mo
r
y
map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
M
eng
hw/riscv: m
i
crochip_
p
fsoc: Map the reserve
d
memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/r
i
scv: microchip_pfsoc:
C
o
nnect the SYSREG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw
/
misc: A
d
d M
i
crochip PolarFire SoC SYSR
E
G module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/ri
s
cv: m
i
cro
c
hip
_
pfsoc: Connect the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/mi
s
c
:
Add Mic
r
oc
h
i
p PolarFire
S
oC IOSCB m
o
d
ule support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
hw/riscv:
m
icr
o
c
h
ip_pfso
c
: Connect D
D
R memory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/m
i
sc: Add Microchip
P
ola
r
Fire S
o
C DDR M
e
mory Control
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/riscv: mic
r
o
chip_pf
s
oc
:
Docu
m
ent
w
here to look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd/sdcard:
Zer
o
out function s
e
l
e
ction
fields
before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Me
n
g
h
w
/intc: Move sifive_pl
i
c
.
h to the include dire
c
tory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: Sort the Kcon
f
ig options in alphabetical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in
Meng
hw/riscv:
D
ro
p
CONFIG_SIF
I
V
E
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: Alway
s
build riscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/ris
c
v: Move sifi
v
e_test model
to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Mov
e
sifive_uar
t
model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Move
riscv_htif mod
e
l to hw
/
char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv:
Mov
e
sifive_plic model to
h
w
/
intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/ri
s
cv:
M
o
v
e sifive_clin
t
m
o
del to h
w
/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifi
v
e
_
gpio model
t
o hw/gpi
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
h
w
/
r
iscv: Move si
f
ive_
u
_otp model to hw/
m
i
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
M
ove
s
ifive_u_pr
c
i m
o
del to hw/mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv:
M
ove sifive_e_prci model to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: sifive_u: Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Me
n
g
hw/riscv
:
clint: Avoid using hard-c
o
ded tim
e
base freque
n
cy
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/r
i
sc
v
: microchip_
p
fsoc: Ho
o
k
G
P
I
O
control
l
er
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: microchip_pfs
o
c: Con
n
ect 2 Cadence
G
EMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm
:
xlnx:
Set all boar
d
s' GEM 'ph
y
-addr' pr
o
perty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w
/net: c
a
dence_gem: Add
a
n
ew 'phy-a
d
dr
'
p
roperty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/
r
i
s
cv
:
microchip_pfsoc:
Con
n
ec
t
a DMA cont
r
ol
l
er
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
h
w
/dma: Add SiFiv
e
platform DMA
c
ontroller emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: microchip
_
p
fsoc: Con
n
ect a Cadence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/sd: Ad
d
Cadenc
e
S
DHC
I
emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
s
c
v
:
microchip_pfsoc: Connect 5 MM
U
ARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/char
:
Add Micro
c
hip PolarFi
r
e
So
C
MMUAR
T
emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Initial suppor
t
for Mi
c
r
o
chip Pola
r
Fire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
t
arge
t
/risc
v
: cpu: Set reset vector based on the con
f
igured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w/riscv: har
t
:
Add a ne
w
'resetve
c
' prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
target/riscv: cpu
:
A
d
d a new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
n
g
gi
t
lab-ci/opensbi
:
U
pdate Git
L
ab CI
t
o bui
l
d
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w/riscv: spike: Change the def
a
ult bio
s
to use gen
e
r
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w
/riscv: Use pre-built bios image of generic platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Mak
e
file: Bui
l
d the generic p
l
atform for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi:
U
pgrade
f
ro
m
v0
.
7 t
o
v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
conf
i
gure: Create symb
o
lic links for pc-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/
r
iscv: sifive_u: Add a dummy L2 cache controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
Correct
t
h
e maximum size of a S
t
andard
C
apacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
Fix inc
o
r
r
ect popul
a
ted
f
unct
i
on switch sta
t
us
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bi
n
Men
g
hw/riscv:
s
if
i
v
e_e: Correct debug block si
z
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n Meng
hw
/
riscv: Modify
MROM size to end at 0x10
0
00
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Me
n
g
hw/r
i
scv: vi
r
t: Sort
t
he So
C
memmap
t
a
b
l
e
entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
M
AINT
A
INERS:
Add an entry
f
or
Ope
n
SBI f
i
r
mware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifive_
u
: Add a du
m
my DDR m
e
mory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/r
i
scv: sif
i
ve_u
:
Sort t
h
e SoC m
e
mmap table entr
i
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
hw/riscv: sifive_u: Support differe
n
t boot so
u
rce per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive: Cha
n
ge SiFive E/U CPU reset ve
c
tor
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target/riscv: R
e
name
I
BEX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: sifive_u: Add a
new pr
o
per
t
y msel for MSE
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sifive_u: Renam
e
s
e
r
i
al p
r
operty
g
et/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: si
f
i
v
e_u: Add reset functionalit
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv
:
sifive_gpio: Do not blindly trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v: sifive_u: Hook a GPIO contro
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_
g
pio: Add a
n
e
w
'
n
gpio' prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv: sifive
_
gp
i
o
:
Clean up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_u:
G
enerate
device
t
ree node
for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
eng
h
w
/riscv: s
i
five_u: Simplify the
G
E
M
I
RQ conn
e
ct code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv
:
openti
t
an: Remove the riscv_ p
r
efix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: sifive_e: Remove the riscv_
prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
risc
v
: Keep the
CPU init routine
n
ames consiste
n
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv:
Gener
a
li
z
e
CP
U
init rout
i
ne for the imac
u
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
ri
s
cv: Ge
n
er
a
lize
CPU
init r
o
utine
for the
g
csu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Genera
l
ize CPU init r
o
utine for
the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Me
n
g
h
w/riscv: v
i
rt: R
e
move the riscv_ prefix of the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
M
eng
hw/ris
c
v: sifi
v
e_u:
R
e
move
the
r
iscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Me
n
g
r
i
s
cv: Chang
e
the d
e
fault behavi
o
r if no -bio
s
option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv: Suppress
t
he error r
e
po
r
t
f
o
r QEMU t
e
sting w
i
th
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin M
e
ng
roms: opensbi:
U
pgra
d
e f
r
o
m v0
.
6 t
o
v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
hw/riscv: Generate correct "mmu-type"
for 3
2
-bi
t
machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
M
eng
riscv/sifi
v
e_u: Add
a
serial p
r
o
per
t
y to the sifive_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2020-03-17
Bi
n
M
e
ng
gitlab-
c
i
.
yml
:
Add jobs to build OpenSBI
f
irmware binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
Bi
n
Meng
riscv: sif
i
ve_u
:
Up
d
ate BIO
S
_FILE
N
AME
f
or 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bin Men
g
ro
m
s: opensbi: Add 32-bit
firmware image for s
i
five_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
Bin Meng
roms: op
e
n
sbi:
U
pgrade
from v0
.
5
t
o v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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2020-03-03
B
in Meng
hw: ne
t
: cade
n
ce_gem: Fix build errors
in
DB
_
PRINT
(
)
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-02-27
Bin Meng
r
iscv: virt: Allo
w
PCI address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin Meng
r
iscv: si
f
i
v
e_
u
:
A
d
d ethernet0 to the
a
liases n
o
de
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: hw
:
Dr
o
p
"clock-frequency" property
o
f cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
r
iscv: Skip che
c
king CSR pr
i
v
ilege level in debug
g
er
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
e
n
g
riscv: sifive_u
:
Upd
a
t
e model and compatible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u:
R
em
o
ve handcrafted
clock
n
odes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
sifive_
u
:
Fix broken GEM supp
o
rt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
ris
c
v: sifive_u: Instantiate OTP
m
emory w
i
th a s
e
rial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: si
f
ive
:
I
mplement a mo
d
e
l for SiFive FU54
0
OT
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
ris
c
v: roms
:
Update de
f
ault bios
for sifive_u machi
n
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv:
sifive_u: Change UART node name in d
e
vice tr
e
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
ri
s
cv: sifive
_
u: Upd
a
te UART base address
e
s a
n
d
IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ri
s
cv: s
i
five_u: Reference PR
C
I cloc
k
s in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: s
i
fiv
e
_u:
Add PRCI block to the SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: sif
i
ve_u: Generate hfcl
k
a
n
d rtcclk
nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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