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target/arm: Enable MTE for user-only
2021-02-11
Bi
n
Meng
hw/block/
n
vm
e
: Fix a build
e
r
r
or in nv
m
e_get_fea
t
ure()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
target/
p
pc: Add
E500 L2CSR0 wr
i
t
e helper
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
hw/net: fsl_etsec
:
Re
v
erse the RC
T
RL
.
RSF logic
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-10
Bin
Meng
hw/ppc: e50
0
:
F
ill
i
n correct <clock-frequency> for
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-10
B
in
M
e
n
g
hw/ppc: e5
0
0: Use a macro for the pla
t
f
orm clock fre
q
uency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi: imx_spi: Correct tx and rx fifo
end
i
anness
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n Meng
h
w/
s
si: imx_spi:
Cor
r
ect the bu
r
st len
g
th
>
32 bit
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n
Meng
hw/ssi
:
imx_spi:
R
ound up the burst lengt
h
to be multiple
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n
M
eng
hw/s
s
i: i
m
x_spi:
R
e
move imx_spi_update_irq(
)
i
n imx_
s
p
i_reset
(
)
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n
M
eng
hw/ssi: imx_spi: U
s
e a ma
c
ro for n
u
mber of
c
h
i
p select
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-25
Bin
Meng
n
e
t: check
s
um:
Introduce
f
i
ne control
over checksum
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n
Men
g
hw/sd: sd
.
h: Cosmetic c
h
an
g
e o
f
using spaces
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/
s
d
:
ssi-sd: Use mac
r
os for the dummy value and tok
e
ns
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
h
w
/sd: ssi-sd: Fi
x
the wro
n
g command i
n
de
x
for
S
TOP_TRANS
M
I
SSION
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-s
d
:
Add a state re
p
res
e
nting Nac
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
in Meng
hw/sd: ssi-s
d
: Suffix a
d
ata blo
c
k with
C
R
C
1
6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
ut
i
l: Ad
d
CRC1
6
(CCITT) ca
l
cul
a
tion routin
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: sd: D
r
o
p
s
d_crc16()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
in Meng
hw/sd: sd: Support CMD59 for SPI mode
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
h
w
/
s
d
:
ssi
-
s
d
: Fix incorr
e
ct
c
ard re
s
ponse sequence
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
B
i
n M
e
ng
t
arget/riscv: R
e
move bu
i
lt-in GDB XML files
for CSRs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Men
g
target/riscv:
Generate the GD
B
XML fi
l
e for CSR re
g
is
t
ers
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin
Meng
target/riscv: Add CSR nam
e
in the CSR functi
o
n
tabl
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
B
in Meng
target/riscv:
M
ake csr_ops[
C
SR
_
T
ABLE_SIZ
E
] external
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin
M
eng
hw/riscv: sifiv
e
_u: Use SIFI
V
E_U_CPU
f
or mc->defaul
t
_cpu_type
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bi
n
Me
n
g
hw/bloc
k
:
m25p80:
D
on
'
t write to flas
h
if w
r
i
t
e is
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
B
i
n Men
g
docs/system: arm:
A
dd sabrelite
b
oard
d
e
s
cription
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin M
e
ng
h
w
/arm: sabrelite: Connect
the
Ethernet PHY at address 6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/msic: imx6_ccm: Correct register value for silicon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Me
n
g
hw/misc: imx6_ccm
:
Update PMU_
M
ISC0 reset value
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin Men
g
ta
r
get/i386: seg_helper:
Correct segment selec
t
or
n
ullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
h
w/sd: Fix 2 GiB card CSD reg
i
ster val
u
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
riscv: microchip_pfs
o
c: Hook the
I
2
C
1 controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/riscv: microch
i
p_pfsoc:
C
orrect D
D
R m
e
mory
m
ap
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/
r
isc
v
:
m
ic
r
ochip_pfso
c
:
M
a
p
the reserv
e
d
m
em
o
ry
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
h
w
/riscv: mic
r
o
c
hi
p
_pfsoc: Connect the
SYSREG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/misc: Add Micr
o
chip P
o
lar
F
ire
SoC
SYSREG mo
d
ule
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microc
h
ip_pf
s
oc:
Connect the IOSC
B
module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Me
n
g
hw/mis
c
: Add Microchip PolarFire S
o
C IOS
C
B module
s
up
p
ort
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/
riscv: micro
c
hip_pfso
c
:
Conne
c
t DDR memory co
n
tro
l
ler
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n M
e
ng
hw/mis
c
: Add Mic
r
ochip Polar
F
ire SoC DDR
Memory Con
t
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: m
i
cro
c
hip_pfsoc: Document wh
e
re t
o
l
ook at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
B
in Meng
hw
/
sd/sdcard: Zero
o
ut functi
o
n selection fields b
e
fore
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Men
g
hw/in
t
c: Move
sifive_plic
.
h
t
o the include director
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Sort the
Kc
o
nfig options i
n
alphab
e
t
i
c
a
l
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
h
w
/ri
s
cv: Dr
o
p CONFIG_
S
IFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: A
l
ways
b
u
i
ld ri
s
cv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
M
eng
h
w/riscv:
M
o
ve sifive_te
s
t m
o
del to h
w
/
mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifi
v
e
_uart mo
d
el to
h
w/c
h
ar
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: M
o
ve
r
isc
v
_hti
f
m
o
del to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv:
M
ove sifive_plic model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: Mov
e
sifive_clint model to
h
w/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Move
s
ifive_gpio model to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w
/ri
s
cv: Move sifive_u_o
t
p model
to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: Move
s
ifive
_
u_prci model
t
o hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv: M
o
ve sifi
v
e
_e_prci
model to hw
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
is
c
v: sifive_u: Co
n
nec
t
a
D
MA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
ri
s
c
v
:
c
li
n
t: Av
o
i
d
us
i
ng hard
-
coded t
i
mebase fre
q
uency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/ris
c
v: microchip_pfsoc: Hook
GP
I
O controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw
/
riscv: mi
c
rochip_pfsoc: Connect 2 Ca
d
ence
G
EM
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
a
rm: xl
n
x: Set
a
l
l boards' GEM 'p
h
y
-addr' prope
r
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
hw/n
e
t: c
a
de
n
ce_ge
m
: Add
a
new '
p
hy-addr'
pro
p
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: micro
c
hip
_
pfsoc: Connect a D
M
A con
t
r
o
ller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: Add SiFi
v
e platform
DMA con
t
roll
e
r
emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in M
e
ng
hw/riscv
:
microchip_pfsoc: Connect a Cadence S
D
HCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw
/
sd: Add Cadence
S
DH
C
I
e
mulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
h
w
/
riscv: microc
h
ip_pfsoc: Con
n
ect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/char:
Ad
d
Microch
i
p PolarFire S
o
C MMUART emu
l
ation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w/riscv: Initial su
p
p
o
r
t for
Micr
o
chip PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
t
arget/risc
v
:
cpu: S
e
t re
s
et vect
o
r b
a
s
e
d on th
e
configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/r
i
s
c
v
: hart: Add a new
'
resetvec
'
p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Men
g
t
a
rg
e
t/
r
iscv:
cpu:
A
dd a new 'res
e
t
vec' pro
p
ert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-
c
i
/opensbi
:
Update Gi
t
Lab
CI to build
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
hw/
r
iscv: spik
e
:
Change
the default bios to u
s
e
gener
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/ri
s
cv: Use pre-bui
l
t bios image of gen
e
ric
platf
o
rm
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
roms/Makef
i
l
e: B
u
ild
the
g
eneric platfor
m
for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in
M
eng
roms/opensbi: Upgrade
f
rom v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
confi
g
u
r
e: Create
s
ym
b
o
lic links
f
or pc-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
hw/
r
iscv: s
i
f
ive_u: Ad
d
a dummy L2 cach
e
controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Correct the m
a
ximum size of
a
Standa
r
d Capacit
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n
M
e
ng
hw/sd: Fix inc
o
rrect popul
a
ted functio
n
switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
h
w
/riscv: sifiv
e
_e: Correc
t
debug block si
z
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv: Modify MROM
siz
e
to
end
at
0
x
1
0000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/r
i
scv: virt: Sort the
S
oC memmap table e
n
t
r
ies
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINT
A
I
N
E
R
S
: Add an e
n
try for Op
e
nSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_u
:
A
d
d a dummy DDR memory cont
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/risc
v
: sifi
v
e
_u:
S
ort
t
he SoC memmap ta
b
le
e
nt
r
ies
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
h
w
/riscv: sifiv
e
_u: Supp
o
rt d
i
f
ferent boot sour
c
e per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: sifive:
Cha
n
g
e
SiFive E
/
U CPU reset vect
o
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
t
a
r
get/r
i
s
c
v
:
Rena
m
e I
B
EX CP
U
i
nit ro
u
t
ine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v:
sifive_u: Add
a
new pr
o
perty msel fo
r
M
SEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
hw
/
riscv: sifiv
e
_u: Rename seria
l
prope
r
ty ge
t
/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
h
w
/
riscv: sifive_u: Add res
e
t
fu
n
ctio
n
ality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Me
n
g
h
w
/riscv: sifive_gpio
:
Do
n
o
t blindly
t
ri
g
g
e
r o
u
tput
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
h
w
/riscv: sifive_u
:
H
o
ok a GPIO
c
o
ntroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_gpio: Add a new 'n
g
pio' pr
o
per
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/
r
iscv: sifi
v
e_gpio: Clean u
p
the
codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: s
i
five_u: Generate device
tr
e
e node fo
r
O
T
P
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/r
i
scv: s
i
five_u
:
Simplify t
h
e GE
M
IRQ
c
onne
c
t
c
ode
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: op
e
n
ti
t
an: Re
m
ov
e
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
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