| commit | 298091f831db1a8f360686369f9760849e90dd03 | |
| author | Bin Meng <bin.meng@windriver.com> | |
| Wed, 10 Feb 2021 02:45:52 +0000 (10 10:45 +0800) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Wed, 10 Feb 2021 03:50:11 +0000 (10 14:50 +1100) | ||
| tree | 146281fe319fe57755b884f700356918a01946dd | treesnapshot (tar.gz zip) |
| parent | ce8e43760e8e7e08c3ab11af874db404d9419a27 | commitdiff |
target/ppc: Add E500 L2CSR0 write helper
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.
Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.
Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/cpu.h | diffblobblamehistory | |
| target/ppc/translate_init.c.inc | diffblobblamehistory |