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hw/riscv: microchip_pfsoc: add QSPI NOR flash
2020-12-10
Bin
Meng
target/
i
3
86:
seg_helper: Correct segment sele
c
tor
nullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin M
e
ng
hw/sd: Fix 2 GiB card CSD
register values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: micr
o
c
hip_pfsoc: Hook the
I
2C1 c
o
nt
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
riscv: microch
i
p
_pfsoc: Correct DD
R
memory map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/riscv: mic
r
oc
h
ip_pfsoc: Map the reserved memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/ris
c
v: mi
c
r
ochi
p
_pfsoc: Connect the
S
YSR
E
G
module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
misc:
A
d
d M
i
crochip P
o
larFire SoC SY
S
RE
G
mo
d
ule
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in
Meng
hw/riscv:
microchip
_
pfsoc: C
o
nne
c
t
the I
O
SCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/misc: Ad
d
Microc
h
ip
PolarF
i
re
S
oC IOSCB module support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw
/
riscv: m
i
crochi
p
_pfsoc
:
Con
n
e
c
t
DDR memory contr
o
l
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw
/
misc: Add Microchip Pola
r
Fire SoC DDR Memo
r
y Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ris
c
v:
m
icro
c
h
ip_p
f
soc
:
Docume
n
t
where to
look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin
M
eng
h
w/sd/sdcard: Zero out f
u
n
c
tion selection f
i
elds before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Me
n
g
h
w/
i
ntc: Move
s
i
five_plic
.
h
t
o
the includ
e
directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw
/
riscv
:
Sort the
K
config options
i
n al
p
h
a
betica
l
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Drop CONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: A
l
ways bu
i
ld
ri
s
cv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Men
g
hw
/
ri
s
cv: Move sifive_t
e
st mod
e
l to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
hw/riscv:
Move sifive_uar
t
mo
d
el to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move r
i
scv_hti
f
model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifive_plic model t
o
hw/
i
ntc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ri
s
cv: Move sifi
v
e_cl
i
nt mod
e
l to hw/i
n
tc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
h
w
/
r
iscv:
M
o
ve sifive_gpio model to
h
w/gpi
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w
/riscv: Move sifive_u
_
ot
p
model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Move
s
ifive_u_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw
/
r
i
scv: Move sifive_e_prci
mod
e
l to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
is
c
v: sifive_u: Connect a
D
M
A con
t
roller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v
: clint: Av
o
id us
i
ng
hard-coded ti
m
ebase
frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: m
i
crochip_pfsoc: Ho
o
k GPIO c
o
ntrollers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
hw/ris
c
v: mic
r
ochip_pfsoc: Connect 2 Caden
c
e GE
M
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/arm: xlnx: Set a
l
l bo
a
rd
s
' GEM 'p
h
y-addr' propert
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/net:
c
ad
e
nce_ge
m
: Add
a
new 'ph
y
-ad
d
r' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: microchip
_
pfsoc: Con
n
ect a DMA co
n
tr
o
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw
/
dma: Ad
d
SiF
i
ve plat
f
orm DMA controller
emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: micro
c
hi
p
_pf
s
oc: Connect a Caden
c
e S
D
HCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd: Ad
d
Ca
d
e
n
ce SDHCI e
m
ulatio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
h
w
/riscv:
microchip_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/cha
r
: Add Microc
h
ip PolarFire
So
C
MMUART emula
t
ion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv:
Initial support f
o
r Micr
o
chip
P
o
larFire So
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
target/riscv: c
p
u: S
e
t
reset vector base
d
on the conf
i
gured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: hart: Add
a new 'r
e
s
e
tvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
ta
r
get/riscv: cpu: Add a
n
ew 'resetvec'
p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
gitlab-ci/opensb
i
: Upda
t
e Git
L
ab CI t
o
build gener
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/
r
iscv: s
p
i
k
e: Cha
n
ge
the de
f
ault
bios to use
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
hw/ri
s
c
v
: Use pre-buil
t
bi
o
s image
of ge
n
eric platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
rom
s
/Makefile: Build the generic p
l
atform for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in
Meng
ro
m
s/
o
pensbi: Upgrade from v0
.
7 t
o
v
0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
configure: Create symbolic links for pc-bios/*
.
e
l
f
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/risc
v
: sifive_u: Add a dummy L2
c
ache controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
C
orrect
the maximum si
z
e of a Standa
r
d C
a
paci
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd:
Fix inco
r
rect populated function switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
B
in
M
eng
hw/riscv: sifive_e: Correct debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Men
g
hw/
r
iscv:
Modify MROM
s
ize t
o
end
a
t 0
x
100
0
0
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n M
e
ng
hw/ri
s
cv: v
i
rt:
S
o
r
t
the SoC memmap ta
b
le entr
i
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
in Meng
M
AINT
A
INERS: Add
a
n ent
r
y
f
or
OpenSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Men
g
h
w
/ris
c
v:
sifive_u: Add a dummy DDR
m
e
m
ory con
t
r
o
ller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv
:
si
f
i
v
e_u: Sort t
h
e S
o
C memmap
table entrie
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifive_u: Support diffe
r
ent boot so
u
rc
e
p
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Men
g
hw/
r
iscv: sifive: C
h
ange SiFive E/
U
CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
target/riscv: Rename IBEX CPU in
i
t
r
o
u
t
ine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv
:
s
i
five_u:
A
d
d a ne
w
property msel for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/r
i
scv: sifive_u:
R
e
name serial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifi
v
e_u: Add reset fun
c
tionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
h
w/riscv: sifive_g
p
io:
D
o n
o
t blindly tr
i
gger out
p
ut
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Meng
hw/ri
s
c
v:
sifive_u: Hook a GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
f
ive
_
g
pio
:
A
d
d a new 'ngpio' prope
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: s
i
fi
v
e
_gpio:
Clean
u
p the c
o
des
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
h
w/riscv: si
f
ive_u: Generat
e
device tree n
o
de for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: si
f
i
v
e_u: Simplify
the
GEM IRQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: opentit
a
n: Remo
v
e the riscv_
p
refix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive_
e
: R
e
move the riscv_ prefi
x
of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Keep th
e
CPU init rou
t
ine names consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
ris
c
v:
G
ene
r
alize CPU init
routine for the imac
u
C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
r
iscv: Generalize CPU init routi
n
e for the gcsu CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gene
r
alize CPU
init
r
ou
t
ine for the b
a
se
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
h
w
/r
i
scv: virt: Remove th
e
riscv_
prefix o
f
the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w
/riscv: sifive_
u
: Remove t
h
e riscv_
p
refix of
t
he
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n
M
eng
riscv: Change the default
b
ehavi
o
r if
n
o -
b
ios option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Me
n
g
riscv: Suppress the error report for QEMU testing wi
t
h
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin M
e
ng
roms: ope
n
sbi
:
U
pgra
d
e from v
0
.
6
to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-04-29
B
in Meng
hw/r
i
scv:
G
en
e
rate correct "mm
u
-typ
e
" for 3
2
-bit m
a
ch
i
nes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-04-29
Bin Meng
riscv/sifive_u:
Add
a s
e
rial p
r
oper
t
y t
o
t
he sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2020-03-17
B
in Meng
gitlab-ci
.
y
m
l: Add jobs to build
O
pe
n
S
B
I firmware b
i
naries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bi
n
M
e
ng
riscv: sifiv
e
_u:
U
pd
a
te BIOS
_
FILENAME
for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
B
i
n
Meng
roms: opensbi: Add 32-bit firmwar
e
image fo
r
sifi
v
e_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2020-03-17
B
i
n Me
n
g
roms: opens
b
i: Upgrade from v0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2020-03-03
Bin M
e
n
g
hw:
n
et: ca
d
enc
e
_gem: Fi
x
build er
r
ors in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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tree
2020-02-27
Bin Meng
r
i
s
c
v
:
virt: Allow PCI addr
e
ss 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin
M
eng
riscv: sifive_u: A
d
d
ethernet0 to
t
he alia
s
e
s n
o
de
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin Meng
riscv:
hw: Drop "clock-frequency" pro
p
erty of cpu
nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2019-10-28
Bin
Men
g
riscv: Sk
i
p
checking CSR
priv
i
lege level
in debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: sifive
_
u: Update model and compa
t
ible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
riscv
:
sifi
v
e_u: Remove handcr
a
ft
e
d
clock nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: sifive_
u
:
Fix br
o
k
e
n G
E
M su
p
po
r
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
r
i
scv: sifive
_
u: Instantiate OTP mem
o
ry with
a s
e
rial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive: Im
p
lement a m
o
del for S
i
Five
F
U5
4
0
OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv: roms: U
p
dat
e
default bios for si
f
i
v
e_
u
machine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u:
Change UAR
T
node name in
d
evice tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
riscv
:
sifive_u: Updat
e
UART base addresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin M
e
ng
riscv: s
i
five_u: Reference PRCI clocks in UART a
n
d
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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