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clock: Remove clock_get_ns()
2020-12-10
Bin
M
eng
tar
g
et/i386: seg_helper: Correct segment selec
t
or nullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
hw/sd: F
i
x 2 G
i
B
c
ard
C
SD
r
egis
t
er values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/r
i
s
c
v: microchip_p
f
soc:
H
oo
k
the I2C1 control
l
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/riscv: microchip_pfsoc: Correct DDR m
e
mor
y
m
ap
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/riscv: micro
c
hip_pfsoc
:
Map the reserv
e
d memo
r
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/riscv: microchip_pfsoc
:
Connec
t
the SYSREG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
Meng
hw/misc: Add Microchip PolarFi
r
e SoC S
Y
SREG mo
d
ule
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/r
i
scv: micr
o
chi
p
_pfsoc:
Connect the IOSCB
m
odule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/m
i
sc:
A
dd M
i
crochip PolarFire
SoC IO
S
CB module support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/riscv: m
i
c
r
ochip_
p
fsoc:
C
o
n
nect DDR memory control
l
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/misc: Add Microchip
P
olarFire SoC
DDR Memory
C
on
t
roller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
r
iscv: microchip_pfsoc: Docum
e
nt where to
l
oo
k
at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd/
s
dcard:
Z
e
ro
o
ut func
t
ion s
e
lec
t
ion fields before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
h
w
/intc: M
o
v
e
sifive_
p
lic
.
h to the
i
nclu
d
e direct
o
ry
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w
/riscv: Sort the Kconfig options in alphab
e
t
ical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/ris
c
v: Drop CONFIG_S
I
FIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Always b
u
ild risc
v
_h
a
rt
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv:
Move sif
i
ve_test model t
o
hw/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Move sifive_uart model to h
w
/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/risc
v
: Move
r
iscv_htif model to hw/
c
har
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/r
i
scv: Move si
f
ive
_
pl
i
c model
t
o hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
hw/ri
s
c
v:
M
o
ve sifive
_
clin
t
model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ri
s
cv: Mov
e
s
i
five_gp
i
o mod
e
l to
h
w/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/r
i
scv: Move sifive
_
u_otp model t
o
hw/m
i
sc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
i
s
cv: Move s
i
f
i
v
e_u_prci mo
d
el to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
h
w/riscv: Move sifive_e_p
r
c
i
model to
h
w/mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v
: sifive_u: Connect
a
DMA con
t
roller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/r
i
scv: clint: Avoid
using h
a
rd-
c
o
d
ed
timebas
e
frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
ris
c
v
:
microchip_p
f
soc: Hook
GPIO controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
h
w
/riscv:
m
icrochi
p
_pf
s
oc: Conne
c
t 2 Cadence G
E
Ms
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/a
r
m: xlnx:
Set all
b
oards' GEM
'
p
hy-a
d
dr
'
prope
r
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
n
et: c
a
dence_gem: Add a new 'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv:
microchip_pfsoc: Co
n
n
ect a DMA con
t
r
o
l
l
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/dma: Add SiFive platform
DMA controller emul
a
tion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
hw/riscv: microchip_pfsoc: Connect a Cadence SD
H
CI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/sd: Add Cadence SDHC
I
emu
l
ation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv:
m
i
croch
i
p_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/ch
a
r: Add Microchi
p
PolarF
i
re SoC
M
MU
A
RT
emu
l
ation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv:
I
nitial support for Microchip PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Me
n
g
tar
g
et/ris
c
v: cpu: Set reset vector
b
ased on t
h
e configu
r
ed
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
h
w/r
i
s
cv: ha
r
t
:
Add
a
new 'res
e
tvec' proper
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
target/riscv: cpu
:
Ad
d
a n
e
w 'resetvec'
p
r
op
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gi
t
lab-ci/opensbi: Upd
a
te GitLab
CI
t
o bu
i
ld generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
hw/riscv
:
spike: Chan
g
e the default
bios to use generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
hw/riscv: Use pre-built bios im
a
ge of
g
eneric platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms
/
Makefile
:
B
u
i
l
d th
e
gene
r
i
c
plat
f
orm for
RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n
M
e
ng
r
o
ms/o
p
ensbi:
Upgrade from v0
.
7
t
o v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
confi
g
ure: Create symbolic li
n
ks fo
r
pc-bios/*
.
e
l
f
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifive_u:
A
dd a d
u
m
my L2 cache
c
ontroller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n
Meng
hw/sd: C
o
rrect
t
he maximum size o
f
a Standard
Cap
a
city
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n Meng
hw
/
sd: F
i
x incorrect po
p
ulated
function swit
c
h status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
B
in
Meng
h
w/ri
s
cv: si
f
iv
e
_e: Correct debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Men
g
hw/r
i
scv:
Modify
MROM size to end at 0x
1
0000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Meng
hw/r
i
scv: v
i
rt:
S
ort the
S
oC memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n
Meng
MAINTAINE
R
S: Add an
ent
r
y for OpenSBI
firmwar
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
ifive_u: Add a
dummy DD
R
m
e
m
o
ry controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
M
en
g
hw/riscv:
s
ifi
v
e_u:
S
ort the So
C
m
e
m
map
t
a
b
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/r
i
scv:
sifive_u: S
u
pport differe
n
t b
o
ot sou
r
c
e
per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
h
w
/riscv: sifive
:
Change SiFive
E
/U CPU r
e
set vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in M
e
ng
tar
g
et
/
riscv
:
Rename IBEX CPU i
n
i
t rou
t
ine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n
Me
n
g
h
w
/riscv: sifive_u: Add a n
e
w property mse
l
for
M
S
E
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
iscv: s
i
five_u
:
R
e
n
a
me
se
r
ial prope
r
ty
g
et/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/
r
is
c
v: sifive_u: A
d
d res
e
t f
u
nctiona
l
ity
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
hw/riscv: sifive_gpio: Do not blindl
y
t
r
igger out
p
ut
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w
/
r
is
c
v
:
sifive_u: Hook a
GPIO con
t
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/ris
c
v: sifive_gpio: Add a n
e
w
'ng
p
io' propert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/riscv:
s
ifive
_
gpio:
Clea
n
up the cod
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sif
i
ve
_
u: Generate
d
e
vi
c
e tree node fo
r
OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v: sifiv
e
_u: Si
m
plify t
h
e GEM
IRQ connect c
o
de
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/ri
s
cv: op
e
ntitan: Remove the
r
iscv_
pr
e
fix
of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/ris
c
v: sifive_e
:
Re
m
ov
e
the riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
ri
s
cv: Keep the
C
PU ini
t
routine names
c
o
nsistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
s
c
v
: Ge
n
eralize CPU init
r
outi
n
e for the imacu C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
iscv
:
G
e
neralize C
P
U
i
nit r
o
u
t
in
e
for the gcsu
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ri
s
cv
:
Generali
z
e CPU i
n
it routi
n
e for th
e
ba
s
e CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
in Men
g
h
w
/
riscv:
virt: Remove t
h
e
r
iscv_
prefix
o
f the machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
hw
/
risc
v
: s
i
five_u: Rem
o
ve the ris
c
v_
prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
riscv: Change the default
b
ehavior if n
o
-bios option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
riscv: Suppress the
e
rror re
p
ort f
o
r Q
E
MU testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bi
n
Meng
roms: opens
b
i: Upgrade from v
0
.
6
t
o v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
M
en
g
hw
/
riscv: Generate c
o
rrect "mmu-type" for 32-bit
m
a
chi
n
es
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bi
n
Meng
riscv/sif
i
ve_u
:
A
dd
a
serial
p
roperty to
t
he sifive
_
u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
gitl
a
b-c
i
.
ym
l
:
A
dd
j
o
b
s
to build Op
e
nSBI fir
m
ware
b
inaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin
M
eng
riscv: sifive_u: Up
d
a
t
e
BIO
S
_F
I
LENAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Me
n
g
roms: opens
b
i:
Add 32-
b
it
firmwa
r
e image for sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms
:
opensb
i
:
U
pgrade from v0
.
5 to
v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin
Meng
hw: net: cadence_gem: Fix buil
d
errors in DB
_
PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: virt
:
Allow P
C
I addres
s
0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin M
e
ng
riscv: sifive_u: Add et
h
ern
e
t0 to the alias
e
s
node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bi
n
Meng
riscv: hw: Dr
o
p "c
l
ock-frequency" property of cpu n
o
des
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: Skip
checking CSR p
r
ivi
l
ege level in deb
u
gger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
s
ifive_u: Update model a
n
d compatible st
r
ings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: sifive_u: Rem
o
ve handcrafted cl
o
ck nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifi
v
e_u: Fix bro
k
en
G
EM supp
o
rt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Instantiate OTP memory with
a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive:
Im
p
lement a model for SiFi
v
e FU540
O
TP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: roms: Update default bios for sifive
_
u machine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
ri
s
c
v
:
s
i
five_u
:
Change
U
ART node
n
ame in devi
c
e tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
riscv: sifive_u: U
p
date
U
ART
b
a
s
e
ad
d
res
s
es and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv:
s
i
fi
v
e_u
:
Reference PRCI clo
c
k
s
i
n
UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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