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hw/riscv: clint: Avoid using hard-coded timebase frequency
2020-09-09
B
in Meng
hw/riscv: c
l
in
t
:
Avoid us
i
ng hard-
c
ode
d
t
imebase
frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv:
m
icroc
h
ip
_
p
f
soc:
H
o
o
k GP
I
O controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/ris
c
v: microchip_pfsoc
:
C
o
nnect 2 Cade
n
ce GE
M
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
hw/arm:
x
lnx: Set all boa
r
ds' GE
M
'
phy-addr'
p
roperty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
n
e
t: cadence_gem: Add a
new 'p
h
y-addr' pro
p
erty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: microchip_pfs
o
c
: Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw
/
dma: Add S
i
Five platf
o
rm DMA controller emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: microchip_pfsoc
:
Connect a Cadenc
e
SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/sd
:
Add C
a
dence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: micro
c
hip_pf
s
oc: Co
n
nect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w/char:
Ad
d
Microc
h
ip P
o
larFire S
o
C MMUART e
m
u
l
atio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Initial support f
o
r Microchip Po
l
arFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
target/riscv
:
c
p
u
: Set rese
t
vect
o
r
b
a
sed on the config
u
red
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
r
i
s
cv:
h
art: Add a
n
ew 'resetvec'
propert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
t
a
rget/
r
iscv: cpu: Add
a
ne
w
'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-ci/opensbi: Update
GitLab CI to buil
d
g
e
neric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: spike: Chang
e
the default
b
ios to use generi
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n
Meng
hw/ri
s
cv:
U
s
e pr
e
-bu
i
lt b
i
os image o
f
ge
n
eric platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Makefile: Bui
l
d the gen
e
ric
platform for RI
S
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi: Upgra
d
e from
v0
.
7 to
v
0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
c
onfigure: C
r
eate symbo
l
ic links for
p
c-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Men
g
hw
/
riscv
:
sifive_u: Add a dumm
y
L
2
ca
c
he controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw
/
sd: Correct
t
he
maximu
m
size of
a
St
a
ndard Capacit
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Fix i
n
correct populated function switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bi
n
Meng
hw/risc
v
: sifive_e: Correct debug
bl
o
ck size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
h
w/r
i
scv:
M
o
dify MRO
M
s
ize to end at 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Meng
hw/riscv: virt: Sort the SoC
m
e
m
map table ent
r
ies
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINTAI
N
ERS: Add
a
n
entry for Op
e
nSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/
riscv: sifive_
u
: Add a dummy
DDR memory
c
ontroll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
iscv: sifive_
u
: Sort the SoC memmap
table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/
riscv:
s
ifiv
e
_u:
Support different boot source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive:
Change SiFive E/U CPU
r
eset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target/riscv: R
e
nam
e
IBEX CP
U
init
r
out
i
ne
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/r
i
scv: sifive
_
u: Add
a
new property msel fo
r
MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w
/risc
v
: s
i
five_u: Rename se
r
ial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
:
sifive_u: Ad
d
reset f
u
nctionali
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv: sifive_gp
i
o:
Do not
blindly trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
hw/ris
c
v: sifive_u: Ho
o
k
a GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv: sifive_gpio: Add a new 'n
g
p
i
o' p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
c
v
:
sifi
v
e_gpi
o
: C
l
e
a
n
up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/r
i
scv: si
f
ive_u
:
Generate d
e
vice tre
e
node for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
sifiv
e
_u
:
Simpli
f
y the GEM
I
RQ
c
onne
c
t
c
ode
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
hw/ri
s
cv: opentit
a
n: Remove the riscv_ p
r
efix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sifive_e: R
e
move the riscv_ prefix of th
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
riscv: Kee
p
the CPU init ro
u
tine names consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv
:
Gen
e
ralize C
P
U
init ro
u
ti
n
e for
t
he
imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
ng
riscv: General
i
ze CPU
init routine for the gcs
u
CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Generalize
CPU init ro
u
tine
for
the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n
Meng
hw/riscv: virt: Remove
the riscv_ prefix of
t
he machi
n
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/riscv: s
i
five
_
u: Remove th
e
riscv_ prefix of
t
he
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n
Meng
riscv: C
h
ange th
e
default behav
i
or if no -bios opt
i
o
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Me
n
g
riscv: Sup
p
ress the error r
e
po
r
t for QEMU testing w
i
th
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bi
n
M
eng
rom
s
: o
p
ensbi: Upgrade from v
0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
B
i
n
M
eng
hw/riscv: Generat
e
correct "mmu-type" for
32-b
i
t
machine
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Me
n
g
ri
s
cv/sif
i
ve_u: A
d
d a
serial property to the sif
i
ve_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
gitla
b
-
c
i
.
yml: Add
jobs to
buil
d
OpenS
B
I f
i
rm
w
are binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
r
iscv
:
sifive_u: Update BIOS_FILE
N
AME fo
r
32-b
i
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms:
o
p
ensbi: A
d
d 32-bit firmware image for sif
i
v
e_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
r
o
ms: opensbi: Upgrade fr
o
m v0
.
5
to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
Bin Meng
hw:
n
et: cade
n
ce_g
e
m
:
Fix bui
l
d errors
in DB_PRI
N
T()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: virt: Allow P
C
I
a
ddre
s
s 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin M
e
ng
riscv: sif
i
v
e_u: Add ethe
r
net0
t
o
the aliases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin M
e
ng
r
i
scv: hw:
D
rop "clock-fre
q
u
ency" property of cpu
n
o
d
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Me
n
g
ris
c
v: Sk
i
p
c
hec
k
ing CSR
privi
l
ege l
e
vel
i
n
d
ebugg
e
r
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
M
en
g
riscv: sifive_u: Update
m
odel
a
nd compatible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv:
s
ifive_u: Re
m
o
v
e
handc
r
a
fted clock nod
e
s
for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Meng
r
iscv: sifive_u: Fix broken GEM supp
o
rt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
risc
v
: sifi
v
e_u: Instanti
a
t
e
O
T
P mem
o
r
y with a serial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
riscv:
sifi
v
e: Implem
e
n
t a
m
o
del for
S
iFi
v
e FU540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: rom
s
: Update default bios
f
o
r
sifive_
u
machine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Me
n
g
r
i
scv: sifiv
e
_u
:
Change UART
node na
m
e in d
e
vice tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sif
i
ve_u: Update UAR
T
base addresses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv: sifive_u: Reference PRCI clocks in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Add PRCI
b
lock to the
SoC
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
M
eng
risc
v
: sifi
v
e_u: Gene
r
ate
h
f
clk and r
t
cclk nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Men
g
r
i
scv: sifive: Implement PRCI model
f
o
r FU
5
40
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Update
PLI
C
hart t
o
pology co
n
fi
g
ura
t
ion
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Men
g
riscv:
sifiv
e
_u
:
U
p
d
a
te hart co
n
figuration to reflect
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
riscv: s
i
five
_
u
:
Set the minimum
n
umber of cpus
to 2
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin M
e
ng
riscv:
h
art: Add a "hartid-
b
ase
"
property to RISC-
V
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Me
n
g
riscv: hart:
Extract hart real
i
ze
to a separate r
o
utine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Me
n
g
risc
v
: Add a sifive_cp
u
.
h t
o
include both E and U cpu
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Meng
riscv: sifive_e: Dro
p
sifive_mmio_emul
a
te()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Meng
riscv
:
sifive
_
e: prci:
Update
the PRCI regist
e
r block
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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tree
2019-09-17
B
i
n Meng
riscv:
s
ifiv
e
_e: pr
c
i
:
Fix a typo of hfxosccf
g
regi
s
ter
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin
M
eng
ri
s
cv: sif
i
ve: Ren
a
me sifive_prci
.
{c, h} to sifive_e_prci
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Men
g
riscv: s
i
five_u: Remove the
unnecessary incl
u
de of
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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tree
2019-09-17
Bin
M
e
n
g
riscv: roms: Remov
e
executable attr
i
but
e
o
f opensbi
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
B
i
n M
e
n
g
risc
v
:
h
w
: Remov
e
the unne
c
essary include
o
f ta
r
get
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
ris
c
v: hw:
Change to u
s
e
qemu
_
l
og_mask(LOG
_
GUEST_ERROR
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2019-09-17
Bin Meng
riscv: hw: Change create_fdt()
t
o
retur
n
void
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
ri
s
cv: hw: R
e
m
o
ve n
o
t needed
PLIC propert
i
es in device
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
riscv: hw: Use qem
u
_
fdt_setprop
_
cell(
)
for property
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2019-09-17
Bin Meng
riscv: hw:
Remove
s
uperfluous "
l
inux, phandle" p
r
op
e
rty
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin Meng
ri
s
cv: hw: Remove duplicated "hw/hw
.
h"
i
n
clusio
n
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: sifive_test:
A
dd
r
eset functional
i
ty
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2019-09-17
Bin
Me
n
g
riscv:
hmp: Add a command to
show
v
irtu
a
l memory mappi
n
gs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2019-09-17
Bin
M
e
ng
risc
v
:
R
e
sol
v
e full path of the given bi
o
s
i
mage
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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|
tree
2019-09-17
Bin Meng
riscv: Add a hel
p
er rout
i
n
e
for finding firmwar
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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2019-09-17
Bin
M
eng
risc
v
: rv32: Root pa
g
e table addre
s
s c
a
n be larger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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