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curl: remove compatibility code, require 7.29.0
2020-12-10
B
in Meng
target/i386:
s
eg_helpe
r
: C
o
r
rect s
e
gment selecto
r
n
u
llificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin
M
eng
h
w
/sd: Fix 2 GiB card
C
SD regist
e
r valu
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Me
n
g
hw/r
i
scv
:
m
i
crochip_pfsoc:
Hook t
h
e I2C1
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Men
g
hw/riscv: micro
c
hip_pfsoc: Co
r
rect DDR memo
r
y
map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ris
c
v: microch
i
p_pfsoc: M
a
p the r
e
s
e
rved memor
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
h
w
/risc
v
: micr
o
chip_pfsoc:
Connect the
SYSREG mo
d
ule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/mis
c
: Add Microchip
PolarFire SoC SYSREG module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w/riscv: microchip_pfsoc: Connect the I
O
SCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Ad
d
M
icrochip PolarFire SoC IOSCB mod
u
le suppo
r
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
h
w
/
r
iscv: microchip
_
p
f
soc: Connect DDR memory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/
m
isc
:
Add Micro
c
hip PolarFire
S
oC DDR Memo
r
y Contr
o
ller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: m
i
c
rochip_pfsoc: D
o
c
umen
t
wher
e
to
look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin
M
en
g
hw/
s
d/sdcard:
Z
ero o
u
t f
u
nct
i
on selecti
o
n
f
ield
s
before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
h
w/intc: Mov
e
s
i
five_
p
l
ic
.
h to the i
n
c
l
ude d
i
r
e
c
to
r
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
hw
/
risc
v
: Sort the Kconfig
opt
i
ons
i
n a
l
phabetical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: Drop CON
F
IG
_
SIF
I
VE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv:
Always bui
l
d
r
iscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Move
s
ifive_t
e
st model t
o
h
w/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/riscv: Mo
v
e sifiv
e
_uart model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/ris
c
v:
Move r
i
scv_htif model to
h
w/ch
a
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sifive_plic m
o
del to
h
w
/
i
ntc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv
:
Move sifive_clint mod
e
l to hw/in
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: Mo
v
e s
i
five_gp
i
o m
o
del to hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Move sifive_u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
ris
c
v: Move
sifive_u_p
r
ci m
o
del to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Move sifive_e_prci
m
odel to
hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: sifive_u: Connect a DMA
contro
l
l
er
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: clint: Av
o
id using hard-coded timebas
e
frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/
r
iscv: microc
h
ip_pfsoc: Hoo
k
G
PIO c
o
ntroller
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: microc
h
ip_pf
s
oc: Connect
2
C
adence GE
M
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/a
r
m
: xlnx: S
e
t all boar
d
s'
G
EM 'phy-a
d
d
r
'
property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
h
w
/net: cadenc
e
_gem: Add a
n
e
w
'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/risc
v
: micr
o
chi
p
_
p
fs
o
c
: Connect a DMA c
o
ntroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/
d
ma: Add SiFive pla
t
form
D
MA control
l
er emulatio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: microchip_pfsoc: Co
n
nect a C
a
den
c
e SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/
s
d: Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv: microchip_pfs
o
c
: C
o
nnect 5 MMUAR
T
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
hw/cha
r
: Add Microchip Pol
a
rFire
SoC MMUART em
u
lation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ris
c
v: Initial support for Micr
o
chip
PolarFire
SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
target/
r
iscv: cpu: Set res
e
t vec
t
o
r
based on the configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: hart: Add
a new 'reset
v
ec
'
p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
target/
r
iscv: cpu:
A
dd a new 'reset
v
ec
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
gitlab
-
ci/opensbi:
Update GitLab C
I
to bu
i
ld generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/
r
i
scv:
s
p
i
ke
:
Change t
h
e d
e
fau
l
t
b
ios
to
use
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
Meng
hw/riscv: Use pr
e
-bu
i
lt b
i
o
s image
of gene
r
ic p
l
a
t
f
or
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
M
e
ng
roms/Makefile:
B
uild
the generic plat
f
or
m
for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
ng
rom
s
/
opens
b
i: Upgra
d
e fro
m
v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
configure: Crea
t
e s
y
mbolic links f
o
r
p
c-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifi
v
e_
u
: A
d
d a
du
m
my L2
c
a
che cont
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Correct t
h
e m
a
xi
m
um size of
a
Standard
Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/
s
d: Fix inco
r
r
ect
popu
l
at
e
d function switch stat
u
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/riscv: sifive_e: Correct debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
eng
h
w/riscv: Modify MROM
s
ize to end at
0
x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv: virt: Sort
t
he SoC memmap table entri
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINTAI
N
ERS: Add an entry for OpenSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: sifiv
e
_u: Add a
d
um
m
y D
D
R
m
emory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in M
e
ng
hw/risc
v
: sifive_
u
: Sort the SoC memmap
t
able ent
r
ies
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
ve_u
:
S
uppo
r
t different
boot
s
ource
p
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv
:
s
i
five: Change SiFiv
e
E/U C
P
U reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
t
a
rget/r
i
scv: Rename IBEX CPU init routi
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: si
f
iv
e
_u: Add a new property msel for MSE
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
hw
/
riscv: sifive_u: Rename serial prope
r
ty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w
/riscv: sifive_u
:
Ad
d
reset functionali
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
hw/
r
iscv: sifive
_
gpio: Do not bli
n
dly tr
i
gger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Hook a GPIO contro
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
h
w/risc
v
: sifive_gpio:
A
d
d a ne
w
'ngp
i
o
' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_gpio: Clean up the
c
odes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
i
s
c
v: sif
i
ve_u:
G
e
nera
t
e devic
e
tree n
o
de for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifi
v
e_u: Si
m
plify
the
G
EM IRQ
co
n
nect c
o
de
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
h
w/riscv: opentitan:
R
emove t
h
e riscv_ prefix of
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sif
i
ve_e:
R
emov
e
the
riscv_ prefix
o
f t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
riscv:
K
eep
the
C
PU init rout
i
ne n
a
mes
consisten
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
r
i
sc
v
:
Ge
n
eralize C
P
U init routine
f
or the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gene
r
aliz
e
CPU
init routine fo
r
the gcsu C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Men
g
ri
s
c
v:
Gene
r
alize CPU in
i
t routine for the ba
s
e CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
ng
hw/ris
c
v: virt: Remo
v
e the
r
i
s
cv_ prefix of
t
h
e mac
h
ine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw
/
ri
s
c
v: sifive_
u
:
R
emo
v
e the
r
isc
v
_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
in M
e
n
g
riscv: Ch
a
nge the
d
efault behavior if
no
-
bios
o
pt
i
on
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-03
Bin Me
n
g
riscv: Suppress the error
report f
o
r QEMU te
s
t
i
n
g with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
roms: op
e
n
sbi: Upgr
a
de
f
rom v0
.
6
to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-04-29
Bin
M
e
ng
hw/riscv: Generate correct "mmu-type" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-04-29
B
i
n Meng
r
iscv/sifiv
e
_
u
: Add a seria
l
proper
t
y to the sifi
v
e_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
B
i
n Meng
g
i
t
lab-c
i
.
yml: Add jobs to build OpenSBI firm
w
are binarie
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Me
n
g
riscv
:
sifiv
e
_u: Upda
t
e
BIOS_FILENAME for 32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
roms: ope
n
sbi: Add 32-bit
f
irmware image for s
i
five_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-17
Bin Meng
r
oms:
opensbi: Up
g
rade from v0
.
5
to v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-03-03
B
i
n
Men
g
hw:
net:
c
adence_gem
:
Fix
build e
r
r
ors
in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Men
g
riscv: virt: Allow PC
I
ad
d
r
ess 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
ris
c
v:
s
ifive_u: Add
eth
e
rne
t
0
to the al
i
ases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: hw:
D
ro
p
"clock-freque
n
c
y
" p
r
operty of
cpu nod
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
riscv: Skip ch
e
cking CSR privilege level in
d
ebugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv: sifive_u: Update model and
c
om
p
atible
s
trings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
riscv: sifive_u: Remove handcr
a
fted clock nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
ris
c
v: s
i
five_u: Fix broken GEM
s
upport
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
riscv: sifive_u: Instantiate OTP
memory with
a s
e
ria
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
ri
s
cv
:
s
i
five
:
Imp
l
e
m
e
nt
a
mod
e
l
f
or S
i
Five F
U
540
O
T
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
M
eng
riscv: roms: Up
d
ate d
e
fault bios
f
or si
f
ive_u
machine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: C
h
ange UART node
name in devi
c
e tree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: sifive_u:
U
pdate U
A
RT base
a
d
dre
s
ses an
d
IRQ
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv
:
sifive_u: Ref
e
r
e
nce
PRC
I
clocks in U
A
RT
a
nd
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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