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hw/ssi: imx_spi: Correct tx and rx fifo endianness
2021-02-02
Bin Men
g
hw/ssi: imx_sp
i
: Correct tx
and rx
f
ifo
e
ndiann
e
ss
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi: imx_spi: Correct
t
he burst
length
>
32 bit
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n Meng
hw/ssi:
i
m
x
_spi: Round up the burst length to be multiple
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
B
i
n Men
g
hw/ssi: imx_spi:
Remove imx_
s
pi_update_irq() in imx_spi
_
re
s
e
t()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi:
i
m
x
_
s
p
i
:
U
s
e a macro for num
b
er o
f
chip selects
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-25
Bin Meng
net: checksum: Introduce fine
c
ontr
o
l over checksum
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n Meng
hw/sd: sd
.
h: Cosmetic
c
hange of us
i
ng spaces
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n
M
eng
hw
/
sd: ssi
-
sd: Use mac
r
os for the dummy value a
n
d tokens
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd
:
ssi-sd: Fi
x
t
he
w
rong c
o
mmand index
f
o
r
STOP_
T
RANSMISSION
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd:
s
si-sd: Ad
d
a state re
p
resen
t
i
ng
N
ac
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin
Meng
hw/s
d
:
ssi-sd
:
Suffi
x
a data block with CR
C
16
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Men
g
util: Add CRC16 (CCIT
T
) calculation
r
outines
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin
M
en
g
h
w/s
d
:
sd: Drop sd_cr
c
1
6
()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/s
d
: sd: Support CMD59 for SPI mo
d
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-sd:
F
i
x
inco
r
rect c
a
r
d
r
e
spon
s
e sequen
c
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
ta
r
get/
r
iscv
:
Remove
b
uilt
-
i
n GDB XM
L
f
iles for CSRs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin
M
eng
tar
g
et/risc
v
: Gene
r
ate
t
h
e GDB XML file
f
or CSR r
e
gisters
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin
M
eng
t
arget/riscv: Add CS
R
name
in the CSR functi
o
n ta
b
l
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
tar
g
et/riscv: M
a
ke csr_ops[CSR_
T
ABLE_SI
Z
E] ext
e
rnal
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
hw/riscv
:
sif
i
ve_u:
Use SIFIV
E
_U_CPU f
o
r mc->default_cpu_type
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
hw/block: m25p8
0
: D
o
n
'
t write to
flash
i
f
write
i
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Men
g
docs/system:
arm: Add sab
r
eli
t
e board description
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
B
in Men
g
hw/arm: sabrelite:
C
onnect
t
h
e Ethernet PHY at address 6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
B
in Meng
hw/m
s
ic: imx6_ccm
:
Cor
r
ect register value
f
o
r
silicon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
B
in Meng
hw/mi
s
c: imx6_ccm: Update PMU_MISC0 r
e
s
e
t valu
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin M
e
ng
target/i386: seg_help
e
r: Correct segment selector
nullif
i
cat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin
M
e
n
g
hw/sd: F
i
x 2 GiB card CSD register
v
alue
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip_pfs
o
c: Hook the
I2
C
1 controll
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
r
iscv:
m
icrochi
p
_pf
s
oc:
C
orrect
D
D
R memory map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: mi
c
roc
h
ip_pf
s
oc
:
Map the
rese
r
ve
d
mem
o
ry
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/risc
v
: microchip_pfsoc: Co
n
nect the
S
Y
S
REG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/misc: Add Microchip PolarFire SoC
SYSREG mod
u
le
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/riscv: micr
o
chip_pfsoc
:
C
o
nnec
t
the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
mis
c
: Add Microchip PolarF
i
re S
o
C IOSCB module
s
u
p
p
o
rt
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Men
g
h
w/ri
s
cv:
m
icro
c
hip_pfsoc:
C
onnect DDR m
e
mo
r
y
c
ontroller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Me
n
g
hw/mi
s
c: Add Mi
c
r
ochi
p
PolarFire SoC DDR Me
m
o
r
y Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ri
s
cv
:
microchip_
p
fsoc: Docu
m
e
n
t
where to
l
o
ok at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw
/
sd/sd
c
a
r
d
: Zero o
u
t function selection fields
b
efore
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin
M
e
n
g
hw/i
n
tc: M
o
ve sifive_p
l
i
c
.
h to
t
h
e
i
ncl
u
de
d
irect
o
ry
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
So
r
t the
Kconfi
g
options in alphabeti
c
al
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: Dro
p
C
ONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w
/riscv
:
Al
w
ays bu
i
ld
r
iscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
e
ng
hw/riscv
:
M
ove si
f
ive_test mo
d
el to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Move s
i
five_uart mod
e
l to hw/ch
a
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
h
w
/riscv: Move ri
s
cv_htif model to hw/
c
har
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/ris
c
v
:
Move
s
if
i
ve_plic model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv:
Move sifive_clint model to hw/i
n
t
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w
/
r
i
s
cv: Mo
v
e sifive_gpio model to hw
/
gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv
:
M
o
ve sifive_u_otp model
to
h
w
/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/r
i
s
c
v
:
Move s
i
five_u_prc
i
model
t
o
hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mo
v
e sifive_e_prci mod
e
l to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/r
i
s
cv: sifive_u: Co
n
nec
t
a
DM
A
con
t
roller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
riscv: clint: Avoid
u
sing
h
a
rd-co
d
ed time
b
a
se f
r
e
q
uency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Men
g
hw
/
riscv:
m
icrochip_pfsoc: H
o
ok GPIO controller
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Men
g
hw/ris
c
v: mic
r
ochip_pfsoc: Connect 2
C
adenc
e
GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ar
m
: xlnx: Set all boards' GEM 'phy-addr' p
r
o
p
erty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
h
w/net: caden
c
e
_gem: Add a new 'phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w
/
riscv:
m
i
crochip_pfsoc: Con
n
e
ct
a DMA
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w
/dma: Add SiFive pl
a
tform DMA co
n
t
r
o
ller
e
m
ulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: microc
h
i
p
_pf
s
oc:
C
o
nn
e
ct a Cad
e
nce
SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd: Add Ca
d
ence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: microchip_pfsoc: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w/char: Add Microc
h
ip PolarFire SoC MM
U
ART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
h
w
/riscv: Initial support f
o
r Microchip Pola
r
Fir
e
SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
targ
e
t/riscv: cpu: Set reset vector
b
ased on the
configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/r
i
scv:
hart: Add a ne
w
'resetvec'
p
roper
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
target/ris
c
v
:
cpu:
A
dd a ne
w
'
r
esetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-ci/o
p
e
nsbi
:
U
p
dat
e
GitL
a
b
CI
to build
gene
r
ic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/ris
c
v: spi
k
e: Cha
n
ge the default bios to
use gene
r
ic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
Meng
hw/riscv: Use pre-built
b
ios
i
m
age of gener
i
c pl
a
tfor
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
roms/Makefile: Build the gener
i
c platform for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in
Meng
roms/opensb
i
:
Upgrad
e
f
rom v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
configure:
C
r
eate symbolic links for pc-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w
/
ris
c
v: sifive_u: Ad
d
a dummy L2 ca
c
he controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw
/
sd: Correct the
m
axim
u
m size of a St
a
ndard
C
apa
c
ity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
eng
hw/sd: Fix inco
r
rect
p
o
pul
a
ted funct
i
o
n s
w
itch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw
/
riscv
:
sifive_e:
C
o
rr
e
ct
deb
u
g blo
c
k
si
z
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv:
M
odify MROM size to end at
0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-07-14
Bin Me
n
g
hw
/
riscv:
v
irt: Sort the S
o
C memmap
t
able
entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n Meng
MAINTAINERS
:
Add an entry for OpenSB
I
firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-06-19
Bin Me
n
g
hw/risc
v
: sifive_u: Add a dummy
D
D
R me
m
o
r
y co
n
trolle
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: sifi
v
e_u:
S
ort
t
he SoC
memmap tab
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv:
s
ifive_
u
:
S
upport dif
f
erent
boot
s
o
urce per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifi
v
e: Change SiFiv
e
E/U CPU re
s
et vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target/riscv: Rename IBEX
C
PU init
ro
u
tine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: si
f
ive_u:
Add a new
p
ro
p
erty ms
e
l for MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
h
w
/
riscv: sifive_
u
: Rename ser
i
a
l pr
o
perty get
/
se
t
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv
:
sifive_u
:
Ad
d
r
eset
f
uncti
o
n
ality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in
Meng
hw/risc
v
: s
i
five
_
gpio: D
o
not
b
l
i
n
d
l
y trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in M
e
ng
hw/riscv: sifive_u: Hook a GPI
O
controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_gpio: Add a new 'ngpio'
prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
hw/riscv: sifive_gpio:
Clean up the co
d
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv:
sif
i
ve_u: Generate de
v
ice t
r
e
e node f
o
r OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Men
g
hw/riscv: sifive_
u
: Simp
l
ify the GE
M
IRQ
connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/r
i
s
c
v: opentitan: Remove the riscv
_
prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_e: Remove
t
he riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
ris
c
v
: K
e
ep the C
P
U
init r
o
utine names consis
t
ent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
en
g
ri
s
cv
:
Gen
e
rali
z
e CPU
init r
o
utine
f
o
r
the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
ris
c
v: Generali
z
e
C
PU init rou
t
ine
for
t
he gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
riscv: Generalize CPU init
ro
u
tine for the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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|
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|
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