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hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INIT
2020-12-10
Bin Me
n
g
ta
r
get/i
3
8
6: seg_helper: Corre
c
t s
e
gment
s
elector null
i
f
i
cat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
B
in Me
n
g
hw
/
sd: Fix 2 GiB
c
ar
d
CSD register value
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microc
h
i
p
_pfsoc: Hook the I
2
C1 controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
n
g
hw/
r
isc
v
:
m
icrochip
_
pfsoc: Correct DDR mem
o
ry map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip_p
f
so
c
: Map the reserved memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: m
i
crochip_
p
fs
o
c:
C
onnect
t
he SY
S
REG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
m
i
s
c: Add Microc
h
ip Pol
a
r
F
ire
SoC SYSREG
m
o
dule
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw
/
riscv: microch
i
p_pfsoc: Conn
e
ct the
I
OSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w/misc: Add Microchip PolarFire
SoC IOSCB module
s
u
ppo
r
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw/risc
v
: micr
o
chip_pfsoc: Connec
t
DDR memor
y
controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/misc: Add Micro
c
hip
Pola
r
Fi
r
e SoC D
D
R
Mem
o
ry Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
h
w/riscv
:
m
i
croc
h
ip_pfsoc: Do
c
ument
w
her
e
to look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw
/
sd
/
sdcard: Zero out function select
i
on fiel
d
s before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Men
g
hw/in
t
c: Move sifive_plic
.
h to the include di
r
ectory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/ri
s
cv:
So
r
t the Kco
n
fig options in al
p
habetical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Drop CONFIG_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv:
A
lways b
u
ild riscv_har
t
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Mov
e
sifive_test
m
odel to hw
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Move
s
ifi
v
e_uart model
t
o hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Move riscv_ht
i
f model
to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
ri
s
c
v: Mov
e
sifive_pli
c
model to h
w
/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv: Mo
v
e
s
ifive_cli
n
t
m
odel to hw/i
n
tc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/ris
c
v: Mov
e
sifive_gpio model to
h
w/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
hw/ri
s
cv: Move sifive_u
_
otp model to hw/mis
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sif
i
ve_u_
p
rci model to
h
w/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
h
w/ri
s
cv: Move
s
ifive_e_prc
i
model to hw/mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/ris
c
v:
s
ifive_u
:
Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv: clint: Avoi
d
using
hard-code
d
timebase frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Men
g
hw/riscv: micr
o
chip_pf
s
oc: Hook GPIO controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: mic
r
ochip_pfsoc
:
Connect 2 Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm: xlnx: Set a
l
l boards' GEM 'phy-addr' p
r
operty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
h
w
/net: cadence_gem
:
Add a n
e
w 'phy-ad
d
r' pro
p
ert
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n M
e
ng
hw/risc
v
: microchi
p
_pfsoc: Connec
t
a
D
MA contro
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/dma: Ad
d
SiF
i
ve
p
latform D
M
A controlle
r
emulati
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
h
w/riscv: micr
o
chip_pfsoc:
C
onnect a Cade
n
c
e SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/sd: Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v:
mi
c
roch
i
p_
p
fsoc: Connect 5 M
M
UA
R
Ts
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
h
w/char:
Add Microchip PolarFire So
C
MMU
A
RT
e
mulati
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/risc
v
:
In
i
tial su
p
por
t
for Microchip PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
t
a
rget/riscv: cpu:
S
et reset vector based on the con
f
igured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/r
i
scv: hart: A
d
d a n
e
w
'
r
es
e
tvec' pro
p
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
target/risc
v
: cp
u
: Add a new 'resetvec' pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
i
n Meng
gitlab-ci/opensbi: U
p
date
GitLab CI to
b
u
ild gen
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: s
p
ike:
Chan
g
e the def
a
ult b
i
os t
o
u
s
e gen
e
ric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
hw/riscv: Us
e
pre-built bios im
a
ge of gen
e
ric pla
t
form
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
ro
m
s/
M
akefile: Build the
generic pla
t
form
f
o
r RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
r
oms/o
p
ensbi:
U
pgrade from v0
.
7
to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
configur
e
:
C
r
eate
s
y
mbo
l
ic link
s
f
o
r
pc-bi
o
s/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
h
w
/riscv: sifi
v
e_u: Add a dummy
L
2
cach
e
controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Co
r
rect the maximum siz
e
of a Standa
r
d
Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin M
e
ng
hw/sd: Fix in
c
orr
e
c
t po
p
ulated function
switch sta
t
us
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/ris
c
v: sifive_e:
C
o
r
re
c
t debug blo
c
k size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv: Modify MROM size to
end
a
t 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw
/
riscv: virt: Sort the SoC memmap
t
able entrie
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n
Meng
M
AINTAINE
R
S: Add an en
t
ry for OpenSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv: sifive_u: Add a
d
ummy DDR memory
controlle
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv: sif
i
ve_u: Sort the SoC memmap tab
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
v
e
_
u:
S
upport d
i
fferent boot source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: sifiv
e
: C
h
a
n
ge SiFive E/U CPU reset
v
ector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
targe
t
/riscv: Rename IBE
X
CPU init r
o
utine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/riscv: sifive_u
:
A
dd
a new
prop
e
r
t
y
msel f
o
r M
S
E
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Rename se
r
i
a
l property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifiv
e
_
u: Add reset f
u
nction
a
lity
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/
r
iscv: sifiv
e
_gpio: Do
not b
l
indly
trigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv:
s
i
f
ive_u: Hook a
G
PIO
con
t
r
o
lle
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio:
A
dd
a
new 'ngpio' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio:
Cle
a
n up th
e
cod
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw
/
ris
c
v: sifive_u: Ge
n
er
a
te device tree node for OT
P
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/riscv: sifi
v
e
_u: S
i
mplify the GEM IRQ connect
code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/r
i
scv: opentitan: Remove the
riscv_ pr
e
fix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_e: Re
m
ove th
e
riscv
_
prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
ri
s
cv: Ke
e
p the CPU
init ro
u
tine na
m
es consisten
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v: Generali
z
e
CPU init
rou
t
ine for
the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
riscv: Generalize
C
PU init
rou
t
i
ne for the gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv:
G
e
ne
r
alize CPU init
r
o
utine
fo
r
the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/
r
iscv: virt: Remove the riscv_ prefix of the mach
i
n
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
hw/ris
c
v
: sifive_u:
Re
m
ove
the ri
s
cv_
prefix of
t
he
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n
Meng
r
iscv: Change th
e
d
e
fault behavi
o
r if no -bios optio
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin
M
eng
riscv: S
u
ppress the err
o
r repo
r
t for QE
M
U te
s
ting with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-04-29
Bin Meng
rom
s
: opensbi: U
p
grade fro
m
v0
.
6 to v
0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-04-29
B
in
M
en
g
hw/ris
c
v: Gene
r
ate correct
"
m
mu-type" for 32-bit machines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-04-29
Bin M
e
ng
riscv/sifive_u
:
Add a serial
p
rope
r
ty to
t
he sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bi
n
Meng
gitlab-c
i
.
y
m
l: Ad
d
jobs t
o
build OpenSBI
f
irmware binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bin
M
eng
riscv: sifive_u: Update B
I
OS_
F
ILENAME for
32-bit
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bin Meng
r
o
ms: opensbi: Add
32-bit fi
r
mware image fo
r
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2020-03-17
Bin Meng
roms
:
opensbi: Upgrade from
v0
.
5 to v
0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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tree
2020-03-03
B
i
n Men
g
h
w
: net: cadence_gem: Fix
build errors in DB_PRIN
T
()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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2020-02-27
B
i
n M
e
ng
riscv:
v
irt: Allow P
C
I address 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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2019-10-28
Bin
M
eng
ris
c
v: sifive_u: Add etherne
t
0 to th
e
ali
a
ses node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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2019-10-28
B
i
n Meng
ris
c
v: hw:
D
rop
"
clock-
f
reque
n
cy" pro
p
e
rty
of cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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2019-10-28
Bin Meng
riscv:
Skip
ch
e
cki
n
g CSR priv
i
lege
l
e
vel i
n
de
b
ugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2019-09-17
Bin Meng
r
iscv: sifive_u: Upd
a
te mode
l
an
d
compatible st
r
ings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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2019-09-17
B
in Meng
riscv
:
sifive_u:
R
emove hand
c
r
a
fted clock
n
odes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
B
in Meng
r
is
c
v: sif
i
ve_u: Fix
brok
e
n GEM su
p
port
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
|
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2019-09-17
B
in Meng
r
i
scv: sifiv
e
_u:
I
n
stantiate OTP
memory with
a
s
erial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin Me
n
g
r
i
scv: sifive: I
m
plemen
t
a model for SiFive FU540 OT
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Men
g
ri
s
cv:
r
oms: U
p
date default bios for sifive_u ma
c
hine
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
commitdiff
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2019-09-17
Bin Meng
riscv: sif
i
ve_u: Change UAR
T
node name in device
tr
e
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
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2019-09-17
Bin
Me
n
g
riscv:
s
ifive_
u
:
Update
U
ART base add
r
esses and IRQs
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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|
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2019-09-17
Bin Meng
riscv:
s
ifive_u: Reference PRCI
c
lo
c
ks
in UART and
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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