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hw/msic: imx6_ccm: Correct register value for silicon type
2021-01-08
B
i
n Meng
h
w/msic: imx6_c
c
m: Corre
c
t register
v
a
l
ue for si
l
icon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
B
in Meng
hw
/
mi
s
c: im
x
6_
c
cm
:
Update PMU_
M
ISC0
re
s
e
t
value
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin M
e
n
g
target/i
3
86: seg_helper:
Correct segm
e
nt selector nu
l
lificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
hw/sd: Fix 2 GiB
c
ard CSD re
g
is
t
er values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/ri
s
cv
:
microchip
_
p
f
soc: Hook the I2
C
1
cont
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv:
mi
c
rochip_pfsoc: Correct DDR memory map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Me
n
g
hw/riscv:
m
icroch
i
p_p
f
soc: Map the re
s
erved memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv:
m
ic
r
o
chip
_
p
f
soc: Con
n
ect the SY
S
REG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Ad
d
Microchi
p
P
o
larFire SoC SYSREG module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: mic
r
ochip_p
f
soc: Con
n
ect the IO
S
CB modu
l
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
m
isc:
Add Microch
i
p
PolarF
i
re SoC I
O
SCB modu
l
e support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
h
w/riscv:
m
icrochip
_
pfsoc: Connec
t
DDR mem
o
r
y co
n
trol
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Add Microchip Pola
r
Fire SoC DDR Mem
o
ry Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: m
i
croc
h
ip_pfsoc: Document w
h
ere
t
o look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
B
i
n Meng
hw/s
d
/sdcard: Z
e
r
o
out functi
o
n s
e
lectio
n
fields before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
B
in Meng
hw/intc: Move sifive_pli
c
.
h
to the include di
r
ectory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv:
S
ort the Kcon
f
ig opt
i
ons in alphab
e
tical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v
:
Drop CONF
I
G_S
I
FIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ris
c
v: Alwa
y
s buil
d
risc
v
_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: Move sifive_test
m
ode
l
to
h
w
/
m
isc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv:
M
ove sifive_u
a
rt model
t
o
h
w/
c
har
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv
:
M
ov
e
ris
c
v
_
htif
m
odel to h
w
/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/
r
is
c
v: M
o
ve sifive_plic m
o
del to h
w
/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in M
e
ng
hw/r
i
scv: Move sifive_c
l
int model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
M
ove
s
ifive_gp
i
o m
o
del to hw/gp
i
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/r
i
scv: Move s
i
five_
u
_otp model to hw
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
ris
c
v: Mov
e
sifive
_
u_
p
r
c
i mo
d
el to
hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/r
i
scv: Move
s
ifive_e_prci
m
odel to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: sifiv
e
_u: Connect a DMA contr
o
ll
e
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/ri
s
cv
:
clint: A
v
oid usi
n
g
h
a
rd-coded ti
m
ebas
e
fre
q
uency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv
:
microchip_p
f
soc: Ho
o
k GPIO contr
o
llers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw
/
risc
v
: microchip_pfsoc: Connect
2 Cade
n
ce GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
a
rm: xln
x
:
Set all bo
a
rd
s
'
GEM 'phy-addr' property
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
h
w
/n
e
t: cadence_ge
m
: Ad
d
a new 'phy
-
a
d
dr' pro
p
e
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/risc
v
: microchip_pfsoc: Connect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
en
g
hw
/
d
m
a
:
A
dd
S
i
Five pla
t
form DMA control
l
er emula
t
ion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/ri
s
cv:
mi
c
ro
c
h
ip_pfsoc: Connect
a
Cadence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd: Add Cade
n
ce SDHCI emu
l
ation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
hw/riscv: microchip_pfsoc: Co
n
nect
5 MMU
A
RTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/char
:
Add Mi
c
r
o
chip PolarF
i
re S
o
C MMUART emu
l
at
i
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Init
i
al support
f
o
r Microchip PolarFire
S
oC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
ta
r
get
/
riscv: cp
u
:
Set reset vector
b
as
e
d
o
n t
h
e configured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in M
e
n
g
hw/riscv: hart: Add a ne
w
'rese
t
vec'
p
roperty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: cpu:
A
dd a
n
ew 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
g
itlab
-
ci/opensbi: U
p
date
G
i
tL
a
b CI to build
g
e
ner
i
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: spike:
C
ha
n
g
e t
h
e
defau
l
t bios
t
o use generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/ri
s
cv: Use p
r
e-built bios image of
g
e
neric pl
a
tfo
r
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/Makefile: Build
t
he
generic platform for RI
S
C
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
ro
m
s/ope
n
sbi: Upgrade from v0
.
7 to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
co
n
figure:
C
re
a
te symbolic
l
inks for pc-bios/*
.
e
l
f
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in M
e
ng
hw/riscv: sif
i
v
e
_
u: A
d
d a
d
u
m
m
y L2 ca
c
he controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bi
n
Meng
h
w
/sd: Correct the maxi
m
um
size of a St
a
nda
r
d Capaci
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Fix incorrect populated function sw
i
t
c
h status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin
M
eng
hw
/
riscv: sifi
v
e_e: Correct
debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
M
e
n
g
h
w/riscv: Modify
MRO
M
siz
e
to end at 0
x
1
0000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
h
w
/riscv: virt: Sort the SoC
m
emma
p
table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
MAINTAINERS: Add
an entry
f
or Op
e
nS
B
I firm
w
are
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifiv
e
_u: Add a dum
m
y
D
DR memory
c
ontro
l
l
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/risc
v
: sifive_u:
Sort
t
he So
C
memmap table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/
r
iscv: si
f
ive_u: Su
p
port di
f
ferent boot sour
c
e per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
ifive:
Change SiFive E/U CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Men
g
target/
r
iscv:
R
e
n
a
m
e IBEX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv: si
f
iv
e
_u: Add a new property msel fo
r
MS
E
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w/riscv: sifiv
e
_u: Rename s
e
rial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
ifive_u: Add r
e
set
func
t
ionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv: sif
i
v
e
_gpio:
D
o not blindly
t
rigger output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
h
w
/riscv:
s
ifive_u: Hook a GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_gpio: Add a n
e
w
'ngpio' pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gp
i
o: Clean up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/ris
c
v: sifive_u:
Ge
n
e
rat
e
de
v
ice tree node for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: S
i
m
p
lify the GEM IR
Q
connect
c
o
de
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
h
w/riscv:
o
pentitan: Remove
t
he riscv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv: sifive_e:
R
emove the riscv_ prefix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
riscv: Keep the CPU init routine names consist
e
nt
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Me
n
g
riscv: Generalize CPU init
routine
f
or th
e
i
macu
C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n M
e
ng
riscv
:
Gener
a
lize CPU init routine for the gcsu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
ris
c
v: Gene
r
alize CPU
init routi
n
e for the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
hw
/
riscv: virt: Remove the riscv_ pre
f
ix of the mac
h
ine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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2020-06-03
B
i
n Meng
hw/riscv: sifiv
e
_u: Re
m
ove the
riscv_ prefix
o
f
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
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2020-06-03
Bin
M
eng
ri
s
cv: Change
t
he
d
efault
b
ehavior if no -bios option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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commitdiff
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2020-06-03
B
i
n Meng
riscv: S
u
ppres
s
the error rep
o
rt f
o
r
Q
E
M
U testing with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
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commitdiff
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tree
2020-04-29
Bin Men
g
roms:
opensbi: Upgrade
f
rom v0
.
6
t
o v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-04-29
Bin Meng
hw/ris
c
v
:
Generate co
r
r
e
ct "mmu-type" for 32
-
bit machin
e
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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2020-04-29
Bin Me
n
g
riscv/sifive_u: Add a serial
p
roperty
to the sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2020-03-17
Bin M
e
ng
gi
t
lab
-
ci
.
y
m
l: Add jobs t
o
b
uild OpenSBI firmware binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-17
B
i
n
Meng
riscv: sifive
_
u: Up
d
at
e
BIO
S
_FIL
E
NAME for
3
2-
b
it
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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2020-03-17
Bin
M
eng
rom
s
: op
e
nsbi: Add 32-b
i
t fi
r
mware image for sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-17
Bin
Me
n
g
roms: opensbi: U
p
g
r
a
de from v0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2020-03-03
B
in Meng
hw: net: cadence_ge
m
: Fix build errors in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-02-27
Bin Meng
riscv: virt: Allow
PCI a
d
dress 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Meng
r
i
scv: sifive_u: Add
ethernet0 to the aliases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin Men
g
riscv: h
w
: Drop
"
clock-frequency" p
r
operty of cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-10-28
Bin
M
eng
riscv:
S
kip checking CSR
p
rivilege level in debugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: si
f
iv
e
_u: Update model and
co
m
patible str
i
n
gs
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
r
i
scv:
sifi
v
e_u: Remove handcrafted clock n
o
des for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
r
i
scv:
s
ifi
v
e_u:
Fix broken GEM supp
o
rt
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Men
g
riscv: si
f
ive
_
u: Instantiate OTP mem
o
ry
w
ith
a
s
e
rial
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifi
v
e: Implement a model for SiFive F
U
540 OTP
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin M
e
ng
ri
s
cv:
roms:
U
pdate defaul
t
bios f
o
r sifiv
e
_u mach
i
ne
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
B
in
Meng
riscv: sifiv
e
_u:
C
h
a
nge UART node name in devic
e
t
ree
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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