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hw/sd: sd.h: Cosmetic change of using spaces
2021-01-24
Bin
M
eng
hw/sd: sd
.
h:
Cosmetic change
of using spaces
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin
Meng
hw
/
sd: ssi-sd: U
s
e
m
acros f
o
r the dummy value and tokens
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bi
n
Meng
hw/sd:
s
s
i-sd: Fix the wrong comma
n
d index for
S
TOP_
T
RANSMIS
S
ION
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-sd: Add
a
state repr
e
senting Nac
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
h
w/sd: ss
i
-sd: Suffix a data
b
lock with CRC16
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
util: Add CRC16 (CCIT
T
) ca
l
culation routines
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n
M
eng
hw/
s
d
: sd: Drop sd_crc16()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd:
s
d
: Suppor
t
CM
D
59 for SPI mode
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
in M
e
ng
h
w
/sd: ssi-sd: Fix incorrect card respon
s
e s
e
quence
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Remove built-in
G
DB XML fil
e
s
for
CSRs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin M
e
n
g
target/
r
iscv:
G
enerate the GDB XM
L
f
i
l
e for CSR regis
t
ers
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
B
in
M
e
ng
t
a
r
g
et/riscv: Add CSR na
m
e i
n
t
h
e
CS
R
function table
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
B
in
Men
g
ta
r
g
e
t/riscv: Make csr
_
ops[CSR_TABLE_SIZE] exter
n
al
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Me
n
g
hw/riscv: si
f
ive_u:
Use SI
F
I
V
E_U_CPU for mc->default_cpu_type
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
hw/bl
o
ck
:
m
2
5
p
80: Don't
w
rite to fla
s
h if write is
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
d
o
cs/system: arm: Ad
d
sabrelite boa
r
d de
s
cr
i
p
tio
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/arm: sabrelite:
Con
n
ec
t
the Ethe
r
n
e
t PHY at addre
s
s
6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
h
w/msic: imx6_ccm:
C
orrect register value fo
r
silicon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin
Men
g
hw/misc: imx6_cc
m
:
Update PMU_MISC0 reset value
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin Meng
targ
e
t/i3
8
6: seg_helpe
r
: Corr
e
ct segment selector nullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
h
w/sd: Fix 2
GiB card CSD
r
egister va
l
u
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/
r
iscv: microchip_pfsoc: Hook the I2C1 controlle
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ri
s
c
v
: microchi
p
_pfsoc:
C
o
rr
e
ct DDR memory
m
a
p
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip_pfsoc: Map the rese
r
ved memor
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip
_
pfso
c
: Conn
e
ct the SYSREG module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
hw/misc: A
d
d
M
i
cro
c
hip PolarFire SoC SYSREG
m
od
u
le
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip
_
pf
s
oc: Connect the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/misc: A
d
d
M
i
c
rochip P
o
larFire
So
C
IOSCB
module suppo
r
t
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/riscv:
m
icrochip_
p
fsoc:
Connect DDR mem
o
ry
c
o
n
t
rol
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/misc: Add
Microchip P
o
l
arF
i
re SoC DDR
M
em
o
ry Contr
o
ller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv:
microch
i
p
_
pf
s
oc: Document wh
e
re
t
o look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin
Me
n
g
hw/sd/sd
c
ard:
Z
e
ro out f
u
nction
s
ele
c
tion fields before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
B
in Men
g
hw/intc: Move
s
if
i
v
e_plic
.
h to the include dir
e
ctory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Sor
t
the Kconf
i
g options in alphabe
t
ical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Drop CONFIG_
S
IFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/
r
isc
v
: Alway
s
build riscv_h
a
rt
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: Mov
e
sif
i
v
e
_tes
t
model t
o
hw/m
i
sc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv
:
M
ove sifiv
e
_uart model to hw
/
cha
r
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/ris
c
v
:
Mo
v
e riscv
_
h
tif m
o
del to
hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/riscv: Move sifive_plic mo
d
el t
o
hw
/
i
ntc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv: Move sifive_clint model to h
w
/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
h
w/riscv: Move sif
i
ve_gpi
o
model to
h
w/gpi
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw
/
riscv: Move sifive
_
u_otp model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
M
ove sifive_u_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ris
c
v: Move sifive_e_prci mo
d
el to
hw/mi
s
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv
:
s
i
five_u
:
Connect a DMA contr
o
ller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv
:
c
lint: Avoid using hard-coded timeba
s
e f
r
equency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v
: microc
h
i
p_pfsoc: Conn
e
c
t 2 Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/arm: xlnx: Set all boards' GEM 'phy-addr' prop
e
r
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/
n
et:
cadence_g
e
m
:
A
dd a new
'
phy-addr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ri
s
cv:
m
icrochip_pfsoc: C
o
n
n
ect a DMA c
o
ntroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
hw/d
m
a:
A
dd SiF
i
ve platform DMA co
n
troller em
u
l
a
tion
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv:
m
icr
o
ch
i
p_pfsoc: Co
n
nect a
C
a
d
ence SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Me
n
g
hw/
s
d:
A
dd C
a
den
c
e
SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: microchip_pfsoc: Conn
e
ct 5 MMU
A
RTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/cha
r
:
Add Microch
i
p Pola
r
Fir
e
SoC MMUART
e
mulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv: Initi
a
l support for Mic
r
och
i
p
PolarFire
SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
t
a
rget/riscv
:
cpu: Set reset vector bas
e
d on t
h
e c
o
nfigured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
h
w/ris
c
v: h
a
rt: Add a
n
ew 'r
e
setvec
'
prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
targe
t
/risc
v
: cpu: Add
a new 'resetvec' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-ci/op
e
nsbi:
Update GitLab CI to b
u
ild gen
e
ri
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: spike: Change the def
a
ult bios to use generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: Use pre
-
built bios imag
e
of gene
r
ic platfo
r
m
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
e
ng
roms/Makefile: Build the generic
p
latf
o
rm for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
r
o
ms/opensbi:
Upgrade from
v
0
.
7
t
o
v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
M
e
ng
c
o
nfigure: Create symboli
c
links f
o
r pc-bi
o
s/*
.
e
l
f
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
hw/riscv: sifive_u:
Add a
d
u
m
my L2 cache c
o
n
troll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd: Corr
e
ct the max
i
m
u
m
s
ize of a Standar
d
C
a
p
acity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/
s
d: Fix incorrect
populated function switch statu
s
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/ri
s
c
v
: sifive_
e
:
Co
r
re
c
t debug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
B
in
M
eng
hw/riscv:
M
odify MR
O
M
size to end
a
t 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
e
ng
hw/riscv
:
virt:
S
o
r
t
the SoC mem
m
ap
tabl
e
entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
in Meng
MAI
N
T
AINERS: Add an entry for Op
e
nSBI firmwa
r
e
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Men
g
hw/ri
s
cv
:
sifive_u: Add a d
u
mmy
DDR memor
y
controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv:
s
i
fi
v
e_u
:
Sort
the SoC memmap tabl
e
entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sif
i
ve
_
u: Support diffe
r
e
n
t boot source
p
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in M
e
ng
hw/riscv: sifive: Change SiFi
v
e E/
U
CPU
res
e
t vec
t
or
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
t
a
rget/
r
iscv: Rename IB
E
X C
P
U
init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-19
Bin Meng
hw/r
i
scv: si
f
ive_u
:
Add a new
p
roperty msel for
MSEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-19
B
in M
e
ng
hw/risc
v
: sifive_u: Rename
s
erial pro
p
erty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-19
Bin Meng
h
w
/
riscv: sif
i
v
e
_
u: Add r
e
set func
t
ionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
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tree
2020-06-19
Bin M
e
n
g
hw/ri
s
cv: sifiv
e
_gpi
o
:
Do n
o
t blindly
t
rigger
o
utput
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
hw/riscv:
s
ifive_u:
H
o
ok
a
GPIO
c
o
n
t
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw
/
riscv: sifive_gp
i
o:
Add a new '
n
g
p
io' p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_gpio: Clean up the
c
odes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sif
i
ve_u: Gen
e
rate device tree n
o
de for
O
TP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
: sifive_u
:
Simplif
y
th
e
G
E
M IRQ
c
o
nnect cod
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
h
w/
r
i
s
cv: opentitan: Remove the riscv_
p
r
efix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Me
n
g
h
w
/riscv: sifi
v
e_e: Remo
v
e
t
h
e
riscv_ prefix of
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: K
e
ep t
h
e CPU init rout
i
ne names cons
i
stent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
ris
c
v:
G
e
neralize CPU
ini
t
rout
i
n
e
for the ima
c
u
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
ri
s
c
v: Gener
a
lize CPU init routine for
t
he gcsu C
P
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ris
c
v:
G
enera
l
ize
C
PU init routine for the base CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
h
w/riscv: virt
:
Rem
o
v
e
the ri
s
cv_ prefix
of the machin
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
h
w/riscv: s
i
five_u: Remove t
h
e risc
v
_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Men
g
r
i
s
c
v: Change
the def
a
u
lt behav
i
or if no -
b
i
o
s
o
ptio
n
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
r
iscv:
Sup
p
ress th
e
err
o
r
repo
r
t
for QEMU t
e
sting with
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin
M
eng
roms: opensbi: U
p
grad
e
from v0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-04-29
Bin Meng
h
w
/riscv: Generate c
o
rrect "mmu-type" f
o
r 3
2
-bit machine
s
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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|
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