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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210112-1' into...
2021-01-08
Bin Meng
d
o
c
s/system: arm: Add sabr
e
li
t
e board
d
e
scription
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/
a
r
m: sabrelit
e
: Connect t
h
e Eth
e
r
n
et PHY at
a
ddress 6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
h
w/msic: imx6_ccm: C
o
r
rect register value for silicon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/misc: imx6_ccm: Upd
a
t
e
P
M
U_MIS
C
0 reset
v
alue
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin Meng
tar
g
e
t
/i
3
8
6
: seg_h
e
lper: Co
r
rec
t
segmen
t
se
l
ector nullif
i
c
at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
hw/sd: Fix
2
GiB card C
S
D r
e
gister values
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ri
s
cv: microchip_p
f
soc: Hook the
I
2C1 control
l
er
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv:
microchip
_
pfsoc: Cor
r
ect
D
D
R
memory map
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ri
s
cv:
m
icrochip_pfsoc: Map the reserved memory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: mi
c
rochip_pfsoc: Connect
the SYSRE
G
m
odule
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
h
w/m
i
sc
:
A
dd Microchi
p
PolarFire SoC SYSREG m
o
dule
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/riscv: microchi
p
_pf
s
o
c
: Conne
c
t the IOSCB module
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/misc: Add Microch
i
p PolarFire SoC IOSCB mod
u
le supp
o
rt
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin
M
eng
hw
/
risc
v
: microc
h
ip_pfsoc:
Con
n
e
ct DDR
m
e
m
ory controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/misc: Add Microchi
p
Polar
F
ire
SoC DDR
M
emory Control
l
er
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/r
i
scv: microchip_pfsoc
:
Docu
m
e
nt
whe
r
e
t
o
look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin
M
eng
hw/sd/sdcar
d
: Zero out function
selection f
i
el
d
s before
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
h
w/intc: Move sifive_plic
.
h to the include directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv:
S
or
t
the K
c
on
f
ig
o
ptions
i
n al
p
habet
i
cal
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv: Dr
o
p
C
ONF
I
G_SIFI
V
E
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Always build
risc
v
_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
hw/ris
c
v
: Move sifive_test
m
odel
to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw
/
risc
v
: Mov
e
sifive_uart model to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mov
e
riscv_h
t
if mo
d
el to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mov
e
s
ifive_plic mo
d
e
l
to hw
/
intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
h
w/ris
c
v: M
o
ve
s
ifive_clint
m
od
e
l to hw
/
intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv:
Move sifive_g
p
io model
t
o hw/gpio
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: Move sifive_u_otp model to hw
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Men
g
hw/r
i
scv:
M
ove sifive_
u
_pr
c
i model to
hw
/
misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv:
Move
s
ifive_e_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
riscv: sifive_u:
Co
n
nect a
D
MA
c
on
t
r
o
ller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv: clint: Avoid us
i
ng hard-coded
timeb
a
se frequen
c
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv
:
microchi
p
_
pfsoc: Hook GPIO controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/ri
s
cv: microchip_pf
s
oc: C
o
nn
e
ct 2 Ca
d
ence GEM
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw
/
arm:
x
lnx:
Set all board
s
' GE
M
'phy-
a
ddr'
p
r
o
per
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n M
e
ng
hw
/
n
e
t: cade
n
ce_
g
e
m
: Add a new 'phy-
a
ddr' property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: microchi
p
_pfsoc
:
Connect a
D
MA contr
o
l
l
er
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/dma:
A
dd SiFive
platform DM
A
contr
o
ller emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv: micr
o
chip_pfsoc
:
Connect a Cade
n
ce SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/sd:
A
d
d Cadence SD
H
CI em
u
lati
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: microchip_pfsoc
:
Con
n
ect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/char
:
Add
Microchip PolarFire S
o
C
MMUART
e
mulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
hw/
r
iscv: In
i
tia
l
s
u
p
p
ort
f
or Microchip
PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv:
c
pu:
S
e
t
r
e
se
t
vector based
o
n the config
u
red
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/riscv:
h
a
rt: Add a new 'r
e
s
e
tve
c
'
p
r
operty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: cpu: Ad
d
a new 'resetv
e
c' pro
p
e
r
t
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-ci/
o
pensb
i
: Update GitLab CI to
b
uild
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv:
spike: Change
t
he
defau
l
t bios to use
g
eneric
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in
Meng
hw/
r
iscv: Use pre-built bios
image
o
f generic platform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/
M
akefi
l
e: Bui
l
d
t
he
g
e
n
eric platfor
m
for R
I
SC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
r
oms/ope
n
s
b
i
: Upgrad
e
from v0
.
7
to v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
configure: Cr
e
ate s
y
mbolic l
i
nks for pc-bios/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
hw/riscv: sifive_u: Add
a dummy L2 cache
c
ont
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd
:
Correct the maximum si
z
e
of
a
Standa
r
d Capacity
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin
Meng
hw/sd: Fix incorrect p
o
pulated function switch status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
hw/r
i
scv: sifive_
e
:
Correct
d
ebug block size
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
n
g
h
w/risc
v
:
Modify MROM size to
end
a
t 0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin Meng
hw/riscv:
virt: Sort the SoC memmap table entr
i
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
MAINT
A
INE
R
S: Add an ent
r
y for OpenS
B
I fi
r
mware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
h
w
/r
i
scv
:
sifive
_
u: Add a dummy DDR memory
c
ontro
l
ler
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_u
:
Sort the
SoC memmap table entrie
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_u
:
Su
p
port different boot
source pe
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
:
s
ifive: C
h
ange SiFive E/U CPU re
s
et v
e
ct
o
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
t
a
rget/r
i
scv: R
e
name IBEX CPU
i
n
i
t rou
t
i
n
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Add a new pro
p
erty msel for MSE
L
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: Rename s
e
ria
l
prope
r
ty get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
iscv: sifive_u: Add
r
ese
t
f
u
nc
t
ionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/riscv:
s
ifive_gpio
:
Do not blindl
y
trig
g
er output
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/r
i
s
cv
:
s
i
five_u: Hook a GPIO contro
l
ler
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_gpio
:
Add a new 'ngpi
o
' prop
e
rty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive_gpio: Cle
a
n up the codes
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Me
n
g
hw/riscv
:
sifive_u: Generate d
e
v
i
ce t
r
ee node
for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/ri
s
cv:
s
i
f
i
v
e_u
:
Simpl
i
fy the G
E
M
I
RQ connect code
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: o
p
entitan: Remove
t
he r
i
scv_ pr
e
fix
of
t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
i
s
cv
:
sifive_e: Re
m
ov
e
the r
i
scv_ prefix o
f
the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
scv: K
e
e
p
t
h
e
C
PU i
n
it ro
u
tine names c
o
nsistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gener
a
l
i
z
e
CPU init routine
f
o
r
the imacu CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
riscv:
G
eneralize CPU init routine
f
or th
e
gcsu CP
U
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
riscv: Genera
l
ize
CPU i
n
it routine for the ba
s
e CPU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
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commitdiff
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tree
2020-06-03
B
in Meng
hw/riscv: virt: Re
m
ove
the riscv_ pre
f
ix of
t
h
e
machine
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
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commitdiff
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tree
2020-06-03
B
i
n Meng
h
w
/riscv: sifive_u:
R
e
move the
r
isc
v
_ prefix of t
h
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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2020-06-03
B
in
M
eng
ri
s
cv:
C
hang
e
the
d
efault
be
h
avior i
f
no
-
bios option
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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commitdiff
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tree
2020-06-03
Bin Meng
riscv: Suppre
s
s th
e
error repo
r
t f
o
r QEMU testing
w
ith
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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commitdiff
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tree
2020-04-29
Bin
Men
g
roms: opensbi: Upgrade from
v
0
.
6 to v0
.
7
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-04-29
Bin Meng
h
w/riscv:
G
enerate correct "mmu-type" for
32-bit
ma
c
hines
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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tree
2020-04-29
Bin Meng
riscv/sifive_u: Add
a
serial pr
o
per
t
y to
t
he
sifive_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
B
i
n Meng
gitlab-ci
.
yml:
A
dd jo
b
s to build
O
penSBI firmwar
e
binaries
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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tree
2020-03-17
Bin Meng
r
i
sc
v
: sifive
_
u
:
U
p
date
BIOS_FIL
E
NAME for 32-b
i
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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tree
2020-03-17
Bin Meng
r
oms:
o
p
ensbi:
A
d
d 32-bit firmware imag
e
for s
i
fiv
e
_u
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-17
Bin
Meng
r
oms:
o
pen
s
bi:
Upgrade fro
m
v
0
.
5 to v0
.
6
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-03-03
B
in Men
g
hw
:
net: cadence_gem:
F
ix
b
uild
e
rrors in DB_PRINT()
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
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commitdiff
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tree
2020-02-27
Bin Meng
r
i
scv: virt:
Allow PC
I
ad
d
ress 0
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
B
in Meng
r
i
s
cv: sifi
v
e_u:
Add eth
e
rnet0 to the a
l
iases node
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin Meng
r
i
scv: hw:
Drop
"
c
lock-frequenc
y
" pr
o
p
erty of cpu nodes
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-10-28
Bin Meng
r
iscv:
S
kip
checking
C
S
R pri
v
ileg
e
lev
e
l in de
b
ugger
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sifive_u: Update mod
e
l and compa
t
ible strings
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
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tree
2019-09-17
Bin Meng
ris
c
v: sifive_u: Rem
o
ve handcrafted
c
lock
nodes for
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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commitdiff
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tree
2019-09-17
Bin Meng
riscv:
s
ifive_u:
Fix broken GEM suppo
r
t
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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2019-09-17
B
in
M
eng
r
i
scv: s
i
five_u: Instant
i
ate OTP
m
emory with a s
e
ria
l
.
.
.
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
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tree
2019-09-17
Bin Meng
riscv:
s
ifive
:
Impleme
n
t
a
m
o
d
el for SiFive FU540
O
T
P
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
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