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hw/sd: ssi-sd: Support multiple block write
2021-02-19
Bin Meng
h
w/sd: ssi-sd
:
Support multip
l
e blo
c
k
write
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
B
i
n Men
g
hw/sd: ss
i
-sd
:
Support s
i
ngle block write
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin
M
eng
hw/sd: Intr
o
duce receiv
e
_ready() callback
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Meng
h
w/sd: sd: Allow
single
/
multi
p
l
e block wr
i
te for SPI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin
M
eng
hw/sd: sd: R
e
move d
u
p
l
icated co
d
es
i
n
s
ingl
e
/
m
ulti
p
le
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin
M
e
n
g
hw/sd: ssi-sd
:
Su
p
port mu
l
t
i
ple block read
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-11
Bin M
e
ng
hw/
b
lock/nvme: Fix a b
u
ild error in
n
vme
_
ge
t
_
f
eature()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
target/pp
c
: Add
E500 L2CSR0 write helper
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
h
w/net: fsl_etsec: Reverse
the RCT
R
L
.
RS
F
logi
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
hw/ppc: e50
0
: Fill in correct <
c
lock-freq
u
ency>
for
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
hw/ppc: e500: Use a ma
c
ro for the
p
latform clock freque
n
cy
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Me
n
g
hw/ssi: imx_spi: Co
r
r
e
ct tx a
n
d rx fifo endiannes
s
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Me
n
g
hw/ssi
:
im
x
_spi: Cor
r
ec
t
the burst len
g
th > 32 bi
t
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi: imx_sp
i
: Round
up the burst length to be m
u
lt
i
ple
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Men
g
hw/ssi: imx_spi: Remove imx_spi_upd
a
te_irq() in imx_spi_res
e
t()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi: im
x
_spi: U
s
e a macro for
n
umber of chi
p
selects
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-25
Bin Meng
net: checks
u
m: Introd
u
c
e
fine
contro
l
o
v
e
r
checksum
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd:
sd
.
h: Cosmetic c
h
an
g
e
o
f using
s
p
a
c
es
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw
/
sd: ssi-sd: Use mac
r
os for
the du
m
my value
a
nd tokens
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin M
e
ng
hw
/
sd: ssi-sd: Fix t
h
e
wrong command index for STOP_T
R
ANSMISSIO
N
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin
M
eng
hw/sd: ssi-sd:
Ad
d
a state
repr
e
senting Nac
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Me
n
g
hw/sd: ssi
-
sd
:
Suffix a
data bl
o
ck with CRC16
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
util: Add CRC16 (C
C
ITT) calculation rou
t
ines
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin
Meng
hw/sd:
s
d: Drop
s
d_crc16()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin
Meng
hw/
s
d: sd: Support
C
MD59 for SPI mode
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd:
s
si
-
sd: Fix incorre
c
t card respo
n
se sequenc
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
ta
r
ge
t
/
r
is
c
v: Remov
e
built-in GDB X
M
L file
s
f
o
r
C
SRs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
B
in Meng
t
a
rget/riscv:
Generate
t
h
e GDB XML file for CS
R
registers
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Add CSR
name in the CSR fun
c
tion ta
b
le
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin
Meng
targe
t
/
r
iscv: Make csr_ops[
C
SR_TABLE_SIZE] exte
r
nal
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
hw/riscv
:
sifive
_
u:
Use
S
IFIVE_U_C
P
U for mc->defaul
t
_c
p
u_type
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
h
w
/blo
c
k: m25
p
80:
D
o
n
'
t wri
t
e
t
o flas
h
if writ
e
i
s
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
B
i
n Meng
docs/syste
m
: arm: Add sabrelite board descripti
o
n
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/arm: sabrelite: Connect the Ethe
r
net PHY at
ad
d
ress 6
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/msi
c
: imx6_ccm: Correct reg
i
ster value for
s
i
l
i
con
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin
M
eng
h
w/mi
s
c: imx6_ccm: Update PMU_MISC0 reset
v
alue
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-12-10
Bin
Meng
target/i38
6
: se
g
_helper
:
Correct
segment se
l
ector nullificat
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
h
w
/sd: Fix
2 GiB card CSD register values
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/risc
v
: m
i
crochip_pfso
c
:
H
o
o
k
the I2C1 controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
riscv: microchip_pfsoc: Cor
r
ec
t
DDR memory
map
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
h
w
/
riscv: microchip_pfsoc: Map the reserve
d
m
e
mory
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
M
e
ng
hw
/
r
i
scv: microchip_pfsoc:
Conne
c
t the SYSR
E
G
module
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Add Microchip P
o
l
a
r
Fir
e
S
o
C
SYSREG mod
u
le
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/riscv: m
i
crochip_pfsoc:
Connect the
IOSCB module
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Add Mi
c
ro
c
hi
p
PolarFire SoC I
O
SCB module support
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/r
i
s
cv
:
mi
c
rochip_pfsoc: Connect DDR m
e
mory
c
ontroller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/m
i
s
c
:
Add Microchip PolarFire SoC
D
DR Memo
r
y
C
ontroller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Me
n
g
hw/riscv: microch
i
p_pfsoc: Docum
e
nt where
to look
a
t
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-26
Bin Me
n
g
hw
/
s
d/sdca
r
d: Zero out function
sele
c
tion f
i
elds before
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
hw/in
t
c
:
Move s
i
five_plic
.
h to the include dire
c
tory
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
h
w/riscv: Sort
the Kconfig
opt
i
ons in alpha
b
e
ti
c
al
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
i
s
cv: Drop CON
F
I
G
_SIFIVE
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ri
s
cv: Al
w
ays build riscv_ha
r
t
.
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
cv: Mov
e
si
f
ive
_
test
m
odel to hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
Meng
hw
/
ri
s
cv: Mov
e
sifive_ua
r
t model
t
o
hw/cha
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/risc
v
: Mo
v
e riscv_h
t
if m
o
d
e
l to hw/
c
har
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
h
w
/riscv:
M
ove s
i
five_pl
i
c mode
l
to hw/intc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move
sifive_clint
model
t
o
h
w/intc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/risc
v
:
M
ove sifive_gpio model
to hw
/
g
p
io
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sif
i
v
e_u_otp model to hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
n
g
h
w
/riscv: Move sifi
v
e_u_prci
m
odel
to
hw/mi
s
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
hw/ris
c
v: Move sifive
_
e_pr
c
i m
o
de
l
t
o
hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/
r
i
s
cv: sifive_u: C
o
nnect a DM
A
c
o
ntroller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: clint: Avoid us
i
ng hard-co
d
ed timebase frequenc
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n M
e
n
g
hw/risc
v
: mi
c
rochip_pfsoc:
H
ook GPI
O
co
n
trollers
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Me
n
g
h
w
/riscv: microchip
_
pfsoc
:
Connect
2
C
a
den
c
e GEMs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/arm: xlnx: Set all boards
'
GEM
'
phy-ad
d
r' prope
r
t
y
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/net: cadence_gem: Add a
n
ew
'
phy-
a
ddr' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
n
g
hw/riscv: mic
r
ochip_pfsoc: Connect a D
M
A controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in M
e
ng
hw/d
m
a: Add SiFive p
l
atform DMA
co
n
trolle
r
emula
t
ion
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
ri
s
cv: mic
r
och
i
p_p
f
soc: Connect a Cadence SDHCI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/s
d
: Add Cadenc
e
S
D
H
C
I emulation
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/
r
i
sc
v
: microchip_p
f
soc: Connec
t
5
MMU
A
RTs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/char:
A
dd Micro
c
h
i
p Pola
r
Fire SoC MMUART
emula
t
ion
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
eng
hw/riscv: Initial
s
upport for
M
icroch
i
p
P
olarFire
S
oC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
target
/
riscv
:
cpu: S
e
t r
e
set vec
t
or bas
e
d
on the configured
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: hart:
Add a new 'resetvec'
p
r
o
perty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target/riscv: c
p
u
:
Add a new 'resetvec
'
property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
gitlab-c
i
/opensbi
:
Update
G
itLab
CI to build generic
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
B
i
n M
e
ng
hw/riscv: spike: Change the defa
u
lt
b
ios
t
o use
gen
e
r
i
c
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
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2020-08-22
Bin M
e
n
g
h
w
/risc
v
: Use pre-b
u
ilt b
i
o
s
image of ge
n
eric platform
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Me
n
g
roms/Makefile: B
u
i
l
d the
g
ener
i
c plat
f
orm fo
r
RI
S
C
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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tree
2020-08-22
B
i
n
Meng
ro
m
s/opensbi: Upgrade from v0
.
7
t
o v0
.
8
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Men
g
configure: Create sy
m
bolic links
f
or pc
-
bi
o
s/*
.
elf
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Me
n
g
hw
/
riscv
:
sifive_u: Add a
dummy L2 cache controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-21
B
i
n Meng
hw
/
s
d
:
Correct the
maximum size of a
S
tand
a
rd Capaci
t
y
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-21
B
i
n Me
n
g
hw/sd: Fix
i
nco
r
rect
p
o
p
ulated funct
i
o
n
switch
s
tatus
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-07-14
Bin Meng
h
w/riscv: Modify MROM size to en
d
at 0x10
0
00
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-07-14
Bin Meng
hw
/
risc
v
: virt:
Sort t
h
e SoC memmap table entries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin M
e
ng
h
w/risc
v
: sifive_u:
A
dd
a
dummy DDR
m
emory
controll
e
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw/ri
s
cv: sifive
_
u: Sort
t
he S
o
C
memmap
ta
b
le
entries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw/
r
iscv: sifive_u: Suppo
r
t
d
i
f
f
erent boot source per
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
in Meng
h
w
/r
i
s
c
v: sifive
:
Change S
i
Fiv
e
E/U CPU reset vector
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
i
n Men
g
ta
r
g
e
t/riscv:
Rename IBEX CPU
init r
o
uti
n
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
i
n Meng
hw/risc
v
: sifive_u: Add a new property msel for MSEL
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Me
n
g
hw/r
i
s
c
v:
si
f
i
ve_u: Rename serial propert
y
get/set
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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tree
2020-06-19
Bin Me
n
g
hw/riscv:
sifive_u: Add
r
e
set func
t
ionali
t
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin
Meng
hw/riscv: sifive_gpio: Do
not blind
l
y
t
rig
g
er
o
utp
u
t
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
i
n Meng
hw/riscv: sifive_u: Hook a G
P
I
O
controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Me
n
g
hw/risc
v
:
sifive_gpio:
A
dd a
new 'n
g
pio'
propert
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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