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hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes
2021-02-10
Bin Me
n
g
hw/ppc
:
e
5
00: Fill in corr
e
ct
<
cl
o
ck-
f
requency> for
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
hw/ppc: e500: Use a mac
r
o for t
h
e pla
t
form clock frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin M
e
ng
h
w/ssi: imx_sp
i
: Corre
c
t tx and rx fifo
e
n
diann
e
ss
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin
M
eng
h
w
/ssi: imx_spi
:
Correct the
b
urst length >
32
b
it
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin M
e
ng
hw/ssi: imx_sp
i
:
Round up the burst length to b
e
multipl
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/
s
si: imx_spi: Remov
e
imx_sp
i
_update
_
irq() in imx
_
spi_
r
e
s
et(
)
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw/ssi: imx_spi: Use a
macro
f
or number of chip selects
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-25
B
in Meng
net: checksum: Int
r
odu
c
e f
i
ne control
o
ver ch
e
cksum
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n Meng
hw/sd:
sd
.
h: Cosmetic change
o
f usi
n
g spaces
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin
M
eng
hw/
s
d
:
s
s
i-
s
d: Use macros for the dummy
v
alue and tokens
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-sd:
Fix the
w
r
o
n
g com
m
and index for STOP_TRAN
S
MIS
S
ION
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-sd: Ad
d
a
state repre
s
entin
g
Nac
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: ssi-sd: S
u
ffix a data b
l
ock
with CRC
1
6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
ut
i
l
: Add CRC16
(CCITT) ca
l
culati
o
n
r
o
u
ti
n
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw
/
s
d
: sd: Drop sd_crc16()
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
Bi
n
Meng
hw/sd: s
d
:
S
u
p
p
o
r
t
CMD59 for SPI mode
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n
Me
n
g
hw/sd: ssi-sd: Fix inc
o
rrect card
r
esponse sequence
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/
r
is
c
v: Remove
bui
l
t-in GDB XML
f
i
les
f
or CSRs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Generate the GDB XML file
f
or CS
R
r
e
g
i
s
ters
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Men
g
t
arg
e
t
/
riscv: Add CSR name in the CSR function table
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
t
a
rg
e
t/riscv:
Mak
e
csr
_
ops[CSR_TABLE_SIZE]
e
x
t
e
r
n
al
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
Bin Men
g
h
w
/
riscv: sifive_
u
: Use S
I
FIV
E
_U_CPU for mc
-
>
default_cpu_typ
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-16
B
i
n
Me
n
g
hw/block: m25p80:
D
on'
t
w
r
ite to flash
i
f
write is
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
docs/system: arm: Add sabrelite board description
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/ar
m
: sabrelite
:
Connect
t
he Et
h
e
rn
e
t
PHY at address
6
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
h
w/m
s
ic: imx6_ccm: Correct register value for silicon
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2021-01-08
Bin Men
g
hw
/
misc: imx6_
c
cm: Update PMU_MISC
0
r
e
set
value
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-12-10
Bin M
e
ng
target/i386: se
g
_helper: Correct segment selector nullificat
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-17
Bin
M
eng
hw/sd: F
i
x
2
G
iB card CSD register val
u
e
s
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchi
p
_pfsoc:
Hook the I2C1
c
ont
r
oller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/ri
s
cv: microchip
_
pfso
c
:
C
orr
e
ct DDR memory ma
p
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
Meng
h
w/riscv:
m
icroch
i
p_pfsoc: Map th
e
r
es
e
r
v
ed
m
emory
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: microchip_pf
s
o
c
: Co
n
nect the SY
S
REG mod
u
le
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc: Add
Mic
r
ochip PolarFire SoC SY
S
REG module
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/r
i
scv:
m
i
cro
c
hip_pfsoc: Connect the IOSCB mo
d
ul
e
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
hw/
m
isc: Add Microchi
p
Pola
r
F
i
re So
C
IOS
C
B module
support
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bi
n
Meng
h
w/riscv: microchip_pfsoc
:
Connect DDR me
m
ory cont
r
oller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
misc: Add Microchip P
o
la
r
F
ire SoC DDR Memor
y
Controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/
r
i
scv: mic
r
ochip_pfsoc: Document wher
e
t
o
look at
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd/sd
c
ard: Ze
r
o out funct
i
on selection f
i
e
l
ds bef
o
re
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
h
w
/intc: Mo
v
e sifive_plic
.
h to th
e
i
n
c
l
u
de directory
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/
r
iscv: S
o
rt the Kconfig optio
n
s in al
p
habetical
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ri
s
cv:
D
rop CONF
I
G
_SIFIVE
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
riscv:
A
lways bu
i
l
d
riscv_hart
.
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ris
c
v: Move
sifi
v
e_tes
t
mod
e
l to hw/m
i
sc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/r
i
s
cv: Move s
i
five_uart mo
d
el to hw/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
h
w/ris
c
v:
M
ove
r
i
scv
_
h
tif m
o
del to
h
w/char
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: Move
sifi
v
e_plic
model to hw/intc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/riscv: Move sifive_clint model
to hw/int
c
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
hw/riscv
:
M
o
ve sifi
v
e_g
p
io model to
hw/g
p
i
o
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
risc
v
:
M
ove sifiv
e
_
u
_
o
tp mode
l
to hw/m
i
sc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: M
o
ve s
i
five_u_prci model to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ri
s
c
v: Move sifi
v
e_e_
p
rci model
to hw/misc
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv
:
s
i
five_u
:
Con
n
ect a DMA controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: clint
:
Avo
i
d using hard-coded
t
ime
b
ase frequency
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/riscv
:
microchip_pfsoc: Ho
o
k GPI
O
controllers
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw
/
riscv: mic
r
o
c
hip
_
p
fsoc: Connect 2 Cadence GEMs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/a
r
m: xln
x
: Set all
b
oar
d
s
'
GEM 'phy
-
add
r
' pro
p
e
r
t
y
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
net: cad
e
nce_gem: Add a
n
ew
'
phy-add
r
' pr
o
perty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv: mi
c
rochip_pfsoc: Connec
t
a DMA
c
ontroller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
e
ng
h
w/dma: Add S
i
Five platform DMA cont
r
oller emu
l
ati
o
n
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/ri
s
cv: m
i
crochip_pfsoc: Connect a Ca
d
enc
e
SDHCI
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd: Add Cadence SDHCI emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
hw/riscv: microchip_pfs
o
c: Connect 5 MMUARTs
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw/char: Add Micr
o
c
h
i
p
Po
l
arFire
SoC MM
U
ART emulation
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv:
I
nitial su
p
p
ort for
M
ic
r
ochip PolarFire SoC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
target/ris
c
v
:
cpu:
S
e
t res
e
t v
e
ctor based on the
c
onfigured
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: har
t
: Add a new 'resetvec' pr
o
p
e
rt
y
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
t
a
rget
/
risc
v
: c
p
u: Add a n
e
w 'rese
t
vec' prop
e
r
ty
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
g
itl
a
b-ci/o
p
e
ns
b
i
:
U
pdate GitLab CI
t
o
build g
e
neri
c
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w/riscv: s
p
ike:
Change the defa
u
lt bios t
o
use generic
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
B
in Meng
hw/riscv: Us
e
pre-b
u
ilt
bios image o
f
g
e
neric
p
latform
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms
/
Make
f
ile: Build the generic platform for RISC
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
roms/opensbi
:
Upgrade from v0
.
7
t
o v0
.
8
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
M
eng
configure: Crea
t
e
s
ymbolic lin
k
s for
p
c
-
bi
o
s/*
.
elf
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-22
Bin
Meng
hw/ri
s
cv: sifive_
u
: Add
a
dum
m
y L
2
cache
c
ont
r
oll
e
r
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
Bin Meng
hw/sd
:
Correct
the
m
aximum
size
of a Standard Capa
c
i
ty
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n Meng
hw/sd: Fix incorr
e
ct populated function s
w
itc
h
status
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-22
Bin Meng
h
w
/risc
v
: sifive_e: Cor
r
ect deb
u
g block s
i
ze
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-07-14
B
in M
e
ng
hw/riscv: Modify MROM size to e
n
d a
t
0x10000
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
B
in
Meng
hw/riscv: vi
r
t: Sort th
e
SoC me
m
map tab
l
e entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Me
n
g
MAINTAINERS:
Add
an ent
r
y for Op
e
nSBI firmware
Signed-off-by:
Bin Meng
<bmeng.cn@gmail.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive_u: Add a du
m
my DDR memor
y
controller
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
i
f
ive
_
u:
S
ort the SoC me
m
map table entries
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/risc
v
:
sif
i
ve_u: Support different boot source per
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/risc
v
:
s
ifive:
C
h
ange
S
i
F
i
v
e E/U CPU reset vector
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in
M
en
g
t
a
rget/riscv
:
Rename I
B
EX CPU init routine
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
e
ng
hw/ris
c
v: si
f
ive_u:
Add
a
new property m
s
el for
M
SEL
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifi
v
e_u: Rename serial property get/set
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
M
e
ng
hw/riscv: sifive
_
u:
Add
reset functionality
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifiv
e
_gpio: Do
n
ot b
l
ind
l
y trig
g
er o
u
tput
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sifive_u: Hook
a
GPIO controller
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
hw/riscv: sifi
v
e_gpio: Add a new 'ngpio
'
property
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv:
s
i
f
i
v
e_
g
pio: Clean up the co
d
es
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_u: G
e
ne
r
ate device tree node
for OTP
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_u:
S
implify the GEM IRQ connec
t
co
d
e
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/
r
iscv: opentit
a
n: Remove
the riscv_
p
r
e
f
i
x
of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv
:
si
f
ive_e: Remove the r
i
scv_ prefix of the
.
.
.
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
r
is
c
v: K
e
ep the CPU i
n
i
t
ro
u
t
i
ne n
a
mes consistent
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
riscv: Generalize CPU in
i
t routine for th
e
imacu
C
PU
Signed-off-by:
Bin Meng
<bin.meng@windriver.com>
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|
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