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hw/sd: sd: Support CMD59 for SPI mode
2021-01-24
Bin Meng
h
w
/sd: sd:
S
up
p
ort
C
M
D59 for SPI mo
d
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/
s
d
:
s
si-sd: Fi
x
incorrect card response sequence
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/ri
s
c
v: Remo
v
e built-in GDB
X
ML fi
l
es fo
r
CSRs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
B
i
n
Meng
ta
r
get/riscv: Generate
th
e
G
D
B
XM
L
fi
l
e fo
r
CSR registe
r
s
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Add CSR
name i
n
the CSR func
t
ion t
a
ble
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin
M
eng
targe
t
/
r
isc
v
: Make cs
r
_ops
[
CSR_
T
ABLE_SIZE] external
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bi
n
Meng
h
w/riscv: s
i
fiv
e
_u: Use SIF
I
VE_U_CPU for mc->default_
c
pu_
t
ype
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin M
e
ng
h
w
/block: m25p80: Don't wri
t
e to flash
i
f
write is
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
docs/system: a
r
m: Add sabrelite board description
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin
M
eng
hw/a
r
m: sabrelite: Con
n
e
c
t the Ethernet P
H
Y at address 6
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
h
w/msic: imx6
_
ccm:
C
or
r
ect register value f
o
r silic
o
n
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin M
e
n
g
hw/misc: imx
6
_
c
cm: Upda
t
e PMU_MISC0 reset v
a
l
u
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-12-10
Bin Men
g
target/i3
8
6: s
e
g_helper: Corr
e
ct segment
se
l
ector nullificat
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
hw/s
d
: Fix 2 GiB
c
ard CS
D
re
g
ist
e
r values
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
h
w/r
i
scv:
m
icrochip_pfs
o
c: Hook the
I
2C1
c
ontroller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/riscv: mic
r
o
c
h
i
p_pfsoc: Correct D
D
R m
e
mory ma
p
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/riscv: microchi
p
_pfs
o
c
:
M
a
p the reserved
memory
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
riscv: microchip_pfsoc: Connect the SYSREG module
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/misc:
Add M
i
c
r
ochip PolarFire SoC SY
S
REG modul
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
r
is
c
v
: mi
c
roc
h
ip
_
pfsoc: Connect the IOSCB module
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
misc: Add Microchip
P
o
larFire SoC IOSCB modul
e
s
upport
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
M
eng
hw/riscv:
m
icr
o
chip_pfsoc: Connect DDR
memory controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
m
isc: Add Microchip Pol
a
rFire SoC
D
DR Memory Controll
e
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/r
i
scv: micr
o
chip_pfsoc: Document wh
e
re
t
o loo
k
at
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
h
w/sd/sdcar
d
: Zero out fun
c
tion se
l
ection
fie
l
ds before
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
hw/
i
ntc: Mo
v
e
sifive_plic
.
h
t
o
th
e
incl
u
de directory
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv:
S
ort t
h
e
K
config optio
n
s i
n
alphabetical
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Drop CONFI
G
_S
I
FIVE
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Always build ri
s
cv_hart
.
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifiv
e
_
tes
t
model to h
w
/
m
isc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Mo
v
e
s
ifive_u
a
r
t
model
t
o h
w
/char
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/riscv:
Move riscv_
h
tif mode
l
to hw/ch
a
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/ris
c
v: Move
s
i
f
iv
e
_pl
i
c
model
to
h
w/int
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: Move sifive_clint
m
od
e
l to hw/intc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: Move sif
i
v
e_gpio
m
o
del to hw
/
g
p
io
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ri
s
cv
:
Move sifive_u_otp
m
od
e
l to hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: Mo
v
e sifive_
u
_prci mo
d
el to hw/mis
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/riscv
:
Move sifi
v
e_e_prci model to hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: sifive_u:
Conn
e
ct
a D
M
A controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: cl
i
n
t
:
Avoid
u
s
i
ng har
d
-cod
e
d tim
e
base fr
e
quency
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v
:
microchip_pfsoc: Hook GPIO co
n
trollers
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/riscv:
m
icroc
h
ip_pfso
c
:
C
onne
c
t 2 Cadence GE
M
s
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/
a
rm: xlnx: Se
t
all
boar
d
s' G
E
M '
p
hy-addr' property
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/net: c
a
dence_gem: Add
a
n
ew 'ph
y
-add
r
' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Men
g
hw/risc
v
: microch
i
p_p
f
soc: Conne
c
t a DMA contr
o
ller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/dma
:
Add
SiFive plat
f
or
m
DMA controller emul
a
t
ion
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
h
w/r
i
scv
:
mic
r
ochip_pfsoc: Connect a Cadence SDHCI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/sd:
Add Cade
n
ce S
D
HCI emulat
i
o
n
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv: m
i
crochip_pf
s
oc: Conn
e
ct
5
MMUA
R
Ts
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/char: Add Microc
h
ip Po
l
arF
i
r
e
SoC MMUART emu
l
ation
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Initial sup
p
ort
f
or Microc
h
i
p
PolarFire So
C
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
targe
t
/
r
i
s
cv:
c
pu: Set
r
e
set v
e
ctor based on the configure
d
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
hw/ri
s
cv: h
a
rt: Add a new 'rese
t
v
ec' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Me
n
g
target/r
i
s
c
v
: cp
u
: Add a new 're
s
etvec
'
prope
r
t
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Men
g
g
itlab-ci/ope
n
s
b
i: Up
d
ate GitL
a
b
C
I to build gene
r
ic
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
h
w
/riscv: spike: Change the default
b
ios to use generic
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
B
in Me
n
g
hw/
r
is
c
v: U
s
e pre-b
u
il
t
bios
im
a
ge of
g
e
ne
r
ic
platform
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
B
in
Meng
roms/Makefile:
B
uil
d
the
generic pl
a
tform for RISC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
roms/o
p
e
n
sbi: Upgrade from v0
.
7 t
o
v0
.
8
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
c
onfigure: Create symbolic
l
i
nks fo
r
pc-bios/*
.
elf
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/riscv: sifive_u
:
Add a dum
m
y L2 cache c
o
ntroller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-21
B
i
n Me
n
g
hw/
s
d: Correct the maximum size of a Sta
n
dard
Capacity
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
eng
hw/sd: Fix i
n
correct populated function switch status
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
Bi
n
Meng
hw/
r
iscv: Modify MROM siz
e
t
o
e
n
d
at 0x10000
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
Bin M
e
ng
hw/riscv:
vi
r
t
:
So
r
t
t
h
e
SoC me
m
map table ent
r
ies
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ris
c
v: si
f
i
v
e_u: Add a dumm
y
DDR memor
y
controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw/riscv: s
i
fi
v
e_u
:
Sort the SoC m
e
mm
a
p
table entries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/ri
s
cv:
s
ifive_u: S
u
p
p
ort
d
ifferent
b
oot
s
o
u
r
ce per
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/ris
c
v: sifive: Change S
i
F
i
ve
E
/U CPU reset vector
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
target/ri
s
cv: Rename IBEX CPU
init r
o
u
t
ine
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: sifive_u
:
Add a ne
w
property msel for MSEL
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
scv:
s
i
five_u: Rename serial pro
p
erty get/set
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv
:
sifive_u: Ad
d
re
s
et fu
n
ctionality
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
r
i
s
cv: sifive_gpio: Do n
o
t blindly trigger output
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/risc
v
: sifive
_
u: Hook a GPIO controll
e
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv:
sifive_gpi
o
: Add a new '
n
g
p
io' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv:
s
i
five_gpio: Clean
up
t
he codes
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
hw/r
i
s
c
v: sifive_u:
G
e
nerate devic
e
tree n
o
de for OTP
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
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2020-06-19
Bin Meng
hw/riscv: si
f
ive_
u
: Simpli
f
y the
G
EM IRQ connect code
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Me
n
g
hw/ris
c
v:
opentitan: Rem
o
v
e the
r
iscv_ p
r
ef
i
x of
t
h
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin
Me
n
g
hw/riscv: sifiv
e
_e: Re
m
o
v
e t
h
e
r
iscv_ prefix of t
h
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
in Meng
riscv:
K
eep the CPU init
routine names con
s
istent
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
r
i
s
cv: Generalize CPU init rou
t
ine for
t
he imacu CP
U
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
riscv: General
i
ze
CPU init
r
outi
n
e for the gcsu CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin
M
eng
riscv: Gen
e
ralize CPU
init rou
t
i
n
e for the base
CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
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2020-06-03
Bin Meng
hw/riscv: virt: Remove t
h
e riscv_ pr
e
fi
x
of the mac
h
in
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
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2020-06-03
Bin Meng
hw/ri
s
cv: sifive_u: Remov
e
the
riscv_
prefix
o
f
the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-03
Bin M
e
ng
r
isc
v
:
Chan
g
e the default be
h
avior
if no -bios op
t
ion
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-03
Bin
Meng
riscv: S
u
ppres
s
the
e
r
r
or re
p
ort for Q
E
MU testing with
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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