repo.or.cz
/
qemu
/
ar7.git
/
search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
first
·
prev
·
next
hw/sd: ssi-sd: Add a state representing Nac
2021-01-24
Bin Men
g
hw/
s
d: ssi-sd: Add a state representing Nac
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw
/
sd: s
s
i-sd: Suffix a dat
a
bl
o
c
k
w
ith CRC16
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Me
n
g
uti
l
: Add CRC16 (CCITT) calc
u
latio
n
routines
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/s
d
: sd: Drop s
d
_
c
rc16()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin
M
e
n
g
hw/sd: sd: Support CM
D
59 for SPI mod
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
h
w/sd: ssi-s
d
:
Fix incorrec
t
c
ard respo
n
se sequence
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv
:
Remove
b
uilt-
i
n GDB
XML files
f
o
r
CSRs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
B
in
M
eng
target/riscv: Generat
e
the
G
D
B XM
L
file for
C
SR registers
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Me
n
g
ta
r
get/riscv:
Add
C
SR n
a
me in the
C
SR functi
o
n t
a
ble
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin M
e
n
g
target/riscv: M
a
ke csr_
o
ps[CSR_TAB
L
E_S
I
ZE] ext
e
rnal
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
B
in Meng
hw/risc
v
: si
f
iv
e
_u
:
Use SIFIVE_U_
C
P
U
for mc-
>
default
_
cpu_typ
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
h
w
/block
:
m25p80: Don't write to flash if writ
e
is
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin
Meng
docs/sys
t
e
m
: arm: Add sabrelite boa
r
d
d
e
s
crip
t
ion
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/arm: sabrelite:
C
onnect the
E
the
r
net PHY at address 6
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin
Meng
hw/
m
sic: imx6_ccm: Correc
t
register value for silicon
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin M
e
ng
hw/misc: i
m
x6
_
ccm: Upda
t
e PMU_MISC0
reset value
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-12-10
B
in Men
g
ta
r
get/i386: seg_he
l
per: C
o
rrect segment selector nullificat
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-17
Bin Meng
hw/sd:
F
ix 2 GiB card CSD register values
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
n
g
hw/
r
iscv: microchip_pfsoc: Hook the I2C1 controll
e
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
hw/ri
s
cv:
m
icroch
i
p_pfsoc: C
o
rr
e
ct DDR memory map
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/riscv: micro
c
hip_pfsoc: Map the
r
e
s
erved memory
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w
/
r
iscv:
m
i
c
roch
i
p
_pfso
c
:
Conne
c
t
t
h
e
S
YSR
E
G
m
o
dule
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Men
g
hw/misc: A
d
d M
i
crochip P
o
larFire SoC SYSREG module
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ri
s
cv: mi
c
rochi
p
_
pfsoc:
C
o
nnect the IOSCB module
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw
/
m
i
sc: Add
Mic
r
o
chip Pol
a
rFir
e
SoC IOSCB
m
od
u
le support
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/ris
c
v: m
i
c
r
ochip_pfsoc: Connect DDR memory c
o
nt
r
olle
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n
M
e
ng
hw/misc: Add Microchip
P
o
l
a
r
Fire SoC DDR Me
m
o
ry
Co
n
trolle
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/ris
c
v: mi
c
roch
i
p_pfsoc: Document
whe
r
e to look at
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-26
B
i
n Meng
hw/sd/sdc
a
rd: Zero out fu
n
ction sele
c
t
ion fields before
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
hw/intc: Move sifive_plic
.
h to the include direct
o
ry
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/
r
i
scv:
S
ort the
K
config options
in
a
lphabetical
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Drop CONFIG_SIFIVE
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/r
i
scv: A
l
wa
y
s bu
i
ld riscv_hart
.
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Me
n
g
h
w/riscv: Mo
v
e s
i
five_test model t
o
hw
/
m
i
sc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw
/
ri
s
c
v: Move sifiv
e
_uart m
o
del to hw/char
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move riscv_htif model to hw/char
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw
/
riscv: Move si
f
ive_plic m
o
del to hw/intc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
h
w
/
ris
c
v: M
o
ve
s
i
f
i
ve_cli
n
t
model to h
w
/
i
n
tc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move sifive
_
gpio
m
odel
t
o
h
w
/gpio
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv:
M
ov
e
sifive
_
u_ot
p
mode
l
t
o
hw/mis
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
hw/risc
v
:
M
o
ve sifive_u_pr
c
i model to hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv:
M
ove sifive_e_
p
r
c
i model to hw/
m
isc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw
/
riscv
:
si
f
ive_u: Connect a DMA controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw
/
riscv: cl
i
nt: Avoid
u
sing har
d
-coded
timebase frequency
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/
r
iscv: microc
h
ip_
p
fso
c
:
Hook GPIO co
n
troll
e
rs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: m
i
c
r
ochip_pfsoc: Co
n
nect 2 Cadenc
e
GEMs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/
a
rm
:
xlnx: Set all
b
oards' GEM 'phy-a
d
dr' pro
p
erty
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/net:
ca
d
e
n
c
e_gem: A
d
d a new 'phy-addr'
p
r
opert
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w
/r
i
s
cv: microc
h
ip_pfsoc: Connect a DMA cont
r
oller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/dma: Add S
i
F
i
ve platform DMA co
n
troller emulati
o
n
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: mi
c
r
o
chi
p
_p
f
soc: Connect a Ca
d
ence SDHCI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w/sd: Add Cadence SDH
C
I
emul
a
t
i
on
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
h
w/risc
v
: microchip_pfso
c
: Connect
5 MMUARTs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
h
w
/char
:
Add Microchip Po
l
arFire SoC MMUART emul
a
tion
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/riscv:
I
n
itial support for Mi
c
ro
c
hip
P
ola
r
Fir
e
SoC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
target
/
riscv: cpu: S
e
t
reset vector b
a
sed on the configured
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
in Meng
hw/ris
c
v: hart: Add a
n
ew '
r
esetvec' pro
p
erty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
target/
r
iscv:
cpu
:
Add a
n
ew
'resetvec' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
gitlab-ci/ope
n
sbi: Update Gi
t
Lab CI to build
g
eneric
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Me
n
g
hw/
r
i
s
cv: s
p
ike
:
Chan
g
e the
d
efau
l
t bio
s
t
o
use
g
eneric
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
hw/r
i
scv: U
s
e
p
re-built bi
o
s image of gener
i
c
platform
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
roms/Makefi
l
e: Build the generic platform for RISC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin Meng
roms/opensbi: Upgrade from
v
0
.
7 to v0
.
8
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bi
n
Meng
configure: C
r
eate symbolic li
n
ks for
p
c-b
i
os/*
.
e
lf
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-22
Bin M
e
ng
h
w
/
risc
v
: sifive_u: Add a dummy L2
c
a
c
h
e
control
l
er
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
e
ng
hw/sd: C
o
rrect
the maximum si
z
e of a Sta
n
dard Capacity
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-08-21
Bin
M
e
ng
hw/sd: Fix inc
o
rrect populated function switch status
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
B
i
n
Meng
hw/riscv: Modify MROM size to end at 0x
1
00
0
0
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-07-14
Bin
M
e
n
g
hw
/
riscv: virt: Sort the So
C
memm
a
p table
entries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Men
g
hw/r
i
scv: sifiv
e
_u: Ad
d
a dummy
D
DR memory cont
r
oller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/
r
i
scv: sifive_u:
Sort the
SoC memmap table entri
e
s
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
sc
v
:
s
i
f
i
ve
_
u:
S
upport
d
iffere
n
t boot source per
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
hw/risc
v
: sifi
v
e: Change SiFive E/U CPU reset vector
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
targe
t
/
riscv: Rename
I
BEX CP
U
in
i
t
routine
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw
/
r
i
scv:
sifive_u: Add a new property
m
se
l
f
o
r
MSE
L
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
h
w
/ri
s
cv: sifive_u: Rena
m
e seri
a
l pro
p
erty get/set
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w
/riscv
:
s
i
five_u: Add reset functio
n
ality
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
h
w/riscv: si
f
ive_gpio:
D
o not blind
l
y tr
i
gger output
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bi
n
Meng
hw
/
riscv: sifive_u: Hook
a
GPIO controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: sifive_g
p
io: A
d
d a n
e
w 'ngpio' p
r
operty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv:
s
ifive_gpio:
Clean
u
p the cod
e
s
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
in M
e
n
g
hw/riscv: sifiv
e
_u:
G
enerate
d
evice
tree node f
o
r
O
TP
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
in Meng
hw/riscv: sifive_u: Sim
p
lify the GE
M
IRQ connect cod
e
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/r
i
sc
v
: opentitan: R
e
move
the r
i
sc
v
_
p
refi
x
of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: si
f
ive
_
e
: Remove t
h
e riscv_ prefix of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
e
n
g
r
iscv: Ke
e
p
the
C
PU init
r
outine names c
o
nsistent
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
r
i
scv:
Gen
e
ralize CPU init
r
outine for the i
m
acu CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Gen
e
r
a
lize CP
U
init routine
f
or the
gcsu
C
PU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
ri
s
cv:
Generalize CPU init routin
e
for
t
he b
a
se CP
U
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
hw/
r
iscv: virt:
R
emove the riscv
_
prefix of the machine
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin Me
n
g
h
w/riscv: sifive
_
u:
Remove
t
he ris
c
v_ prefix of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bi
n
Meng
ri
s
cv: Change
t
he
d
efault
behavior if no -bios option
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin
Meng
riscv: Suppress
t
he error rep
o
rt for QEMU testing
with
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree