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hw/sd: sd: Only SDSC cards support CMD28/29/30
2021-02-19
Bin M
e
ng
hw/sd: sd: Only SDSC c
a
rds
support
C
MD28/29/30
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin
Meng
h
w
/sd: sd: Fix addre
s
s check in sd_er
a
se()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Meng
hw
/
sd: ssi-sd: Handle the rest command
s
with R1b resp
o
n
se
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Meng
hw
/
s
d
: ssi-sd
:
Fi
x
ST
O
P_T
R
A
N
S
MISSION (CMD12) respo
n
se
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
B
in Meng
hw/sd
:
ssi-sd
:
Fix SE
N
D_I
F
_COND (CMD8
)
response
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
B
in Meng
hw/sd: ssi-sd: Supp
o
rt mul
t
iple
b
lock wri
t
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Meng
hw/sd
:
ssi-sd: Support sing
l
e block write
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
B
in Meng
hw/sd: Intr
o
duce r
e
ceive_re
a
dy() callbac
k
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Men
g
hw/sd:
s
d: Allow sin
g
le/multiple block wr
i
te for SPI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Meng
hw/sd: sd: Remove duplicated codes in sing
l
e/mult
i
ple
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-19
Bin Me
n
g
hw/sd: ssi
-
s
d
: Support multiple bl
o
c
k r
e
ad
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-11
Bin
M
e
n
g
hw/block/nvme: Fix a buil
d
erro
r
in nvme_get
_
feature()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin M
e
ng
target/ppc: Add E500 L2
C
S
R0 write helpe
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin Meng
hw/net: fsl_etse
c
: Rever
s
e
t
h
e RCTRL
.
RSF logic
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
Bin M
e
ng
h
w
/p
p
c: e500: F
i
ll i
n
co
r
r
e
ct <cloc
k
-frequency> for
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-10
B
i
n M
e
n
g
hw/ppc: e500: Use a ma
c
ro for the pla
t
form clock frequency
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Men
g
hw/ssi:
i
mx_spi
:
Co
r
rect tx and r
x
fifo
e
ndianness
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin M
e
ng
hw/ssi: imx_spi:
C
orrect
the burst l
e
ngth > 32
bi
t
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin M
e
ng
hw/ssi: imx_spi
:
Ro
u
nd up th
e
burs
t
l
ength to
be
m
u
ltiple
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bi
n
Meng
hw/ssi: imx_spi: Rem
o
ve imx_spi_up
d
a
te_irq() in imx_spi_reset(
)
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-02-02
Bin Meng
hw
/
ssi:
imx
_
spi: Use a macro
f
or
number of chip sel
e
cts
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-25
Bi
n
Meng
net: ch
e
cksum: Intr
o
duce fi
n
e
c
ontrol
o
ver ch
e
ck
s
um
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/s
d
: sd
.
h: Cosmetic change of us
i
ng s
p
aces
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin M
e
ng
hw/sd:
s
si-sd: Use
macros for the
d
ummy
v
a
l
u
e
and to
k
en
s
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n M
e
ng
h
w/sd: ssi-sd
:
F
ix the
w
rong command inde
x
for STOP_T
R
A
N
SMISS
I
ON
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Me
n
g
hw/sd: ssi-sd: Add a state
r
epre
s
e
nting Nac
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
B
i
n Meng
h
w/sd: ss
i
-sd: Suffix a data block with CRC16
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bi
n
Meng
uti
l
:
Add CRC16 (CCITT) c
a
l
c
ulation routines
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Men
g
hw/sd:
s
d: Drop
sd_crc16()
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
hw/sd: sd
:
Sup
p
or
t
CMD59 f
o
r
S
PI mode
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-24
Bin Meng
h
w
/sd: ssi-s
d
:
Fix inc
o
rrect card response sequence
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
tar
g
et/riscv
:
Re
m
ove
b
uilt
-
in
GDB
X
M
L files for C
S
Rs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Gener
a
te the GDB
XML file
f
o
r
CS
R
re
g
ist
e
rs
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/
r
iscv: Add
C
SR name in the CSR f
u
nction tabl
e
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
target/riscv: Mak
e
cs
r
_ops[CSR_TA
B
LE_SI
Z
E]
extern
a
l
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bi
n
Meng
hw/riscv: s
i
fi
v
e
_
u: Use SIFIVE_U_CPU for
m
c-
>
d
e
f
ault_cp
u
_type
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-16
Bin Meng
hw/block: m25p
8
0:
D
on'
t
write to
f
lash if write is
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin
Meng
docs/s
y
stem
:
ar
m
: Add
sa
b
r
elite board d
e
scription
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/arm: sabrelit
e
: Connect the Eth
e
rne
t
PHY a
t
address 6
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/msic
:
imx6
_
ccm: C
o
r
rect registe
r
val
u
e for silicon
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2021-01-08
Bin Meng
hw/
m
isc: imx6_ccm:
Update PMU_MISC0
r
es
e
t value
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-12-10
B
in Meng
target/i386: seg_helpe
r
:
Correct segment selector null
i
ficat
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-17
B
in Meng
hw
/
sd:
F
i
x
2
G
i
B card CSD register
v
a
lues
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Me
n
g
hw/riscv
:
micr
o
chip_pfsoc:
H
ook the
I
2C1 controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
in Meng
hw/riscv
:
mi
c
rochip_pfsoc
:
Correct DDR mem
o
ry map
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Meng
hw/riscv: micro
c
hip_pfso
c
: M
a
p the rese
r
ved
memory
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
h
w/ri
s
cv: mic
r
ochip_pfsoc:
C
o
nnect the SYSREG
m
o
d
ule
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin Meng
hw/
m
isc: Add Microch
i
p
P
olarFire So
C
SYSREG
mod
u
le
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Me
n
g
hw/ri
s
cv: microchi
p
_pfsoc: Connect the
I
OSCB mo
d
ule
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
B
i
n Meng
hw/misc: A
d
d Microch
i
p PolarFire SoC IOSCB modu
l
e
supp
o
rt
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/riscv:
microc
h
ip_pf
s
oc: Conne
c
t DDR memor
y
controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin M
e
ng
hw/misc: Add Microchip PolarFire
SoC
D
DR Me
m
ory Co
n
t
r
o
l
ler
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-11-03
Bin
Me
n
g
hw/risc
v
: microc
h
ip_
p
f
s
oc: Documen
t
where to look at
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-26
Bin Meng
hw/sd/sdcard: Z
e
ro out function sele
c
t
ion fields bef
o
re
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-10-22
Bin Meng
h
w
/
i
nt
c
:
M
ove sifi
v
e
_
p
lic
.
h to the includ
e
directory
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Men
g
hw/ris
c
v:
Sort the K
c
onfig
o
ptions
i
n
alphabe
t
i
c
al
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/r
i
scv: Drop CONFIG_SIFIVE
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Alw
a
ys build riscv_har
t
.
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
h
w
/
riscv
:
Move sifive_
t
est mo
d
el t
o
hw/misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
eng
hw/riscv: Move sifive_uart model to hw/c
h
a
r
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Meng
hw/riscv: Move riscv_htif model to hw/c
h
ar
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/riscv: Move sifive_plic model to hw/intc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n M
e
ng
hw/ri
s
cv: Move sifive_clint model to
h
w/int
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
en
g
hw/riscv: Move sifive_gpio model t
o
hw/gpio
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bi
n
Meng
hw/ri
s
cv: Mov
e
si
f
ive_
u
_otp model t
o
h
w
/
misc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/riscv: Move s
i
f
i
ve_u_prc
i
model to hw
/
m
i
sc
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw
/
riscv: Move s
i
five_
e
_
prci model
to h
w
/mi
s
c
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv:
si
f
ive_u: Connec
t
a DMA c
o
ntroller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
hw
/
riscv:
c
li
n
t
:
Avoid usi
n
g hard-c
o
ded time
b
ase frequen
c
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ris
c
v: micro
c
hip_pf
s
oc: Hook GPIO controllers
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n
M
eng
hw/riscv
:
micr
o
chip_pf
s
oc: Conn
e
ct 2 Cadence GEMs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/ar
m
: xlnx: Set all boa
r
ds' GEM '
p
hy-add
r
'
p
ropert
y
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/n
e
t:
ca
d
en
c
e_g
e
m: Add a new 'phy-
a
dd
r
' p
r
oper
t
y
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
Me
n
g
hw/riscv: microchip_pfsoc: Conn
e
ct a D
M
A controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin Meng
hw/d
m
a
:
Add S
i
Five platform DMA
co
n
tr
o
l
ler emulation
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin M
e
ng
hw/riscv: microchip_pfsoc: Connec
t
a Cadence S
D
HCI
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
Bin
M
eng
h
w
/sd: Add Cadence S
D
HCI emulation
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Me
n
g
h
w/riscv:
m
icrochip_pfsoc: Connect
5 MMUARTs
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-09-09
B
i
n Meng
hw/char: Add
M
icrochip Pola
r
Fire SoC MMUART emu
l
a
t
i
on
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-09-09
Bin Meng
hw/riscv: Initia
l
s
u
pport for Mi
c
rochip Pol
a
rFire SoC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-09-09
Bin Meng
target
/
riscv: cpu
:
Set reset
v
ector based on the
c
on
f
i
g
ured
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-09-09
Bin
Meng
hw/riscv: h
a
rt: A
d
d a new 'resetvec' p
r
operty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-09-09
Bin Meng
target/riscv: cpu:
Add a new 'resetvec' property
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Meng
gitlab-ci/opensbi: Update GitLab CI to buil
d
generi
c
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
B
i
n
Meng
hw/r
i
scv: s
p
ike: Change the default b
i
os to use gen
e
ric
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Meng
hw/riscv:
Use pre
-
built bios image of
g
en
e
ric platform
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
B
in Meng
roms/M
a
k
efile
:
Build the gener
i
c pl
a
t
f
orm for
R
ISC
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Men
g
roms/ope
n
sbi: Upgrade
f
rom v0
.
7 to
v
0
.
8
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin Meng
co
n
figur
e
: Create s
y
mbo
l
ic links
f
or p
c
-bio
s
/*
.
elf
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-22
Bin
M
eng
hw/ris
c
v: sifive_u: Add a
d
ummy L
2
cache con
t
rol
l
er
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-21
Bin Meng
hw/sd: Correct the ma
x
imum size of a Standard Capac
i
ty
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-08-21
Bi
n
M
e
ng
hw
/
sd: Fix
i
n
correct popu
l
ated fun
c
tion s
w
i
tch st
a
tus
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-07-14
Bi
n
Me
n
g
h
w/riscv: M
o
d
ify MROM s
i
ze to
end at 0x10
0
00
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-07-14
Bin
M
e
ng
hw/riscv: virt:
S
ort the
SoC memmap t
a
ble e
n
tr
i
es
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw/riscv:
s
ifi
v
e_
u
: Add a dummy D
D
R me
m
o
r
y controller
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw/r
i
scv:
s
ifive_u: Sort t
h
e S
o
C memmap
t
ab
l
e en
t
ries
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
B
i
n Meng
hw/riscv
:
s
i
f
ive_u:
S
upport diffe
r
ent
boot source pe
r
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw
/
riscv: sif
i
ve: Change SiFive E
/
U CPU rese
t
v
e
ctor
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
tar
g
et
/
riscv: Renam
e
IBEX CPU init rout
i
ne
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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2020-06-19
Bin Meng
hw/
r
is
c
v: sifive_u: Add a new proper
t
y
msel for MS
E
L
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
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