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target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
2021-01-16 Bin Mengtarget/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Green Wanhw/misc/sifive_u_otp: handling the fails of blk_pread...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Menghw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Atish Patratarget/riscv/pmp: Raise exception if no PMP entry is...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Atish PatraRISC-V: Place DTB at 3GB boundary instead of 4GB
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Sylvain Pelissiergdb: riscv: Add target description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Xuzhou Chenghw/block: m25p80: Implement AAI-WP command support...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Bin Menghw/block: m25p80: Don't write to flash if write is...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisriscv/opentitan: Update the OpenTitan memory layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Use the CPU to determine if 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...7788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Set XLEN independently from target
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu_helper: Remove compile time XLEN...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...55d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...90066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...35b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: fpu_helper: Match function defs in HELPER...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...73a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: sifive_u: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: spike: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: virt: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: boot: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: virt: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Expand the is 32-bit check to support more...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisintc/ibex_plic: Clear interrupts that occur during...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
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2020-12-18 Alex Richardsontarget/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Yifei Jiangtarget/riscv: Fix the bug of HLVX/HLV/HSV
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Xinhao Zhanghw/core/register.c: Don't use '#' flag of printf format
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Vitaly Woolhw/riscv: microchip_pfsoc: add QSPI NOR flash
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Anup Patelhw/riscv: sifive_u: Add UART1 DT node in the generated DTB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-14 Alistair Francisintc/ibex_plic: Ensure we don't loose interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...828e7c3f85293a09a65b12.1605136387.git.alistair.francis@wdc.com
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2020-11-14 Alistair Francisintc/ibex_plic: Fix some typos in the comments
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...67ac909926368d1bcb7cf5.1605136387.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francishw/intc/ibex_plic: Clear the claim register when read
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Split the Hypervisor execute load helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the hyp load and store functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the HS_TWO_STAGE flag
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Set the virtualised MMU mode when doing...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...53f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Add a virtualised MMU Mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com
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2020-11-03 Xinhao Zhangtarget/riscv/csr.c : add space before the open parenthesis '('
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Hook the I2C1 controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Correct DDR memory map
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Map the reserved memory...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect the SYSREG module
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC SYSREG module...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect the IOSCB module
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC IOSCB module support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Connect DDR memory controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/misc: Add Microchip PolarFire SoC DDR Memory Controller...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Bin Menghw/riscv: microchip_pfsoc: Document where to look at...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add sifive_plic vmstate
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add V extension state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add H extension state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add PMP state description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Add basic vmstate description of CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Yifei Jiangtarget/riscv: Merge m/vsstatus and m/vsstatush into...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Anup Patelhw/riscv: virt: Allow passing custom DTB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-03 Anup Patelhw/riscv: sifive_u: Allow passing custom DTB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Green Wanhw/misc/sifive_u_otp: Add backend drive support
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Green Wanhw/misc/sifive_u_otp: Add write function and write...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Yifei Jiangtarget/riscv: raise exception to HS-mode at get_physical_address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Load the kernel after the firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: Add a riscv_is_32_bit() function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: Return the end address of the loaded firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3262248b040563716628b2.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: sifive_u: Allow specifying the CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Georg Kotheimertarget/riscv: Fix implementation of HLVX.WU instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Georg Kotheimertarget/riscv: Fix update of hstatus.GVA in riscv_cpu_do_inte...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Georg Kotheimertarget/riscv: Fix update of hstatus.SPVP
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Bin Menghw/intc: Move sifive_plic.h to the include directory
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francisriscv: Convert interrupt logs to use qemu_log_mask()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
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2020-09-25 Alistair Franciscore/register: Specify instance_size in the TypeInfo
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...61d266557d3173bf160524.1598376594.git.alistair.francis@wdc.com>
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2020-09-25 BALATON Zoltanload_elf: Remove unused address variables from callers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Sort the Kconfig options in alphabetical...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Drop CONFIG_SIFIVE
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Always build riscv_hart.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_test model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_uart model to hw/char
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move riscv_htif model to hw/char
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_plic model to hw/intc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_clint model to hw/intc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_gpio model to hw/gpio
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_u_otp model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_u_prci model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Move sifive_e_prci model to hw/misc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: sifive_u: Connect a DMA controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: clint: Avoid using hard-coded timebase frequency
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Hook GPIO controllers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/arm: xlnx: Set all boards' GEM 'phy-addr' property...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/net: cadence_gem: Add a new 'phy-addr' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect a DMA controller
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/dma: Add SiFive platform DMA controller emulation
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect a Cadence SDHCI...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/sd: Add Cadence SDHCI emulation
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/char: Add Microchip PolarFire SoC MMUART emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: Initial support for Microchip PolarFire SoC...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Mengtarget/riscv: cpu: Set reset vector based on the configured...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Menghw/riscv: hart: Add a new 'resetvec' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-09-09 Bin Mengtarget/riscv: cpu: Add a new 'resetvec' property
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU